2011-03-06 00:20:21 +00:00
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/* Blackfin Trace (TBUF) model.
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2014-01-01 03:54:24 +00:00
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Copyright (C) 2010-2014 Free Software Foundation, Inc.
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2011-03-06 00:20:21 +00:00
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "config.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_cec.h"
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#include "dv-bfin_trace.h"
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/* Note: The circular buffering here might look a little buggy wrt mid-reads
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and consuming the top entry, but this is simulating hardware behavior.
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The hardware is simple, dumb, and fast. Don't write dumb Blackfin
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software and you won't have a problem. */
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/* The hardware is limited to 16 entries and defines TBUFCTL. Let's extend it ;). */
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#ifndef SIM_BFIN_TRACE_DEPTH
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#define SIM_BFIN_TRACE_DEPTH 6
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#endif
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#define SIM_BFIN_TRACE_LEN (1 << SIM_BFIN_TRACE_DEPTH)
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#define SIM_BFIN_TRACE_LEN_MASK (SIM_BFIN_TRACE_LEN - 1)
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struct bfin_trace_entry
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{
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bu32 src, dst;
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};
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struct bfin_trace
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{
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bu32 base;
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struct bfin_trace_entry buffer[SIM_BFIN_TRACE_LEN];
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int top, bottom;
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bool mid;
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/* Order after here is important -- matches hardware MMR layout. */
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bu32 tbufctl, tbufstat;
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char _pad[0x100 - 0x8];
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bu32 tbuf;
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};
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#define mmr_base() offsetof(struct bfin_trace, tbufctl)
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#define mmr_offset(mmr) (offsetof(struct bfin_trace, mmr) - mmr_base())
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2011-03-15 20:44:11 +00:00
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static const char * const mmr_names[] =
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{
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2011-03-06 00:20:21 +00:00
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"TBUFCTL", "TBUFSTAT", [mmr_offset (tbuf) / 4] = "TBUF",
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};
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#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>")
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/* Ugh, circular buffers. */
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#define TBUF_LEN(t) ((t)->top - (t)->bottom)
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#define TBUF_IDX(i) ((i) & SIM_BFIN_TRACE_LEN_MASK)
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/* TOP is the next slot to fill. */
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#define TBUF_TOP(t) (&(t)->buffer[TBUF_IDX ((t)->top)])
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/* LAST is the latest valid slot. */
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#define TBUF_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 1)])
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/* LAST_LAST is the second-to-last valid slot. */
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#define TBUF_LAST_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 2)])
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static unsigned
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bfin_trace_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_trace *trace = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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value = dv_load_4 (source);
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mmr_off = addr - trace->base;
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HW_TRACE_WRITE ();
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switch (mmr_off)
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{
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case mmr_offset(tbufctl):
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trace->tbufctl = value;
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break;
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case mmr_offset(tbufstat):
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case mmr_offset(tbuf):
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/* Discard writes to these. */
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break;
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default:
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dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_trace_io_read_buffer (struct hw *me, void *dest,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_trace *trace = hw_data (me);
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bu32 mmr_off;
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bu32 value;
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mmr_off = addr - trace->base;
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(tbufctl):
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value = trace->tbufctl;
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break;
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case mmr_offset(tbufstat):
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/* Hardware is limited to 16 entries, so to stay compatible with
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software, limit the value to 16. For software algorithms that
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keep reading while (TBUFSTAT != 0), they'll get all of it. */
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value = MIN (TBUF_LEN (trace), 16);
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break;
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case mmr_offset(tbuf):
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{
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struct bfin_trace_entry *e;
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if (TBUF_LEN (trace) == 0)
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{
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value = 0;
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break;
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}
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e = TBUF_LAST (trace);
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if (trace->mid)
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{
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value = e->src;
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--trace->top;
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}
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else
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value = e->dst;
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trace->mid = !trace->mid;
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break;
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}
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default:
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while (1) /* Core MMRs -> exception -> doesn't return. */
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dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
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break;
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}
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dv_store_4 (dest, value);
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return nr_bytes;
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}
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static void
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attach_bfin_trace_regs (struct hw *me, struct bfin_trace *trace)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_COREMMR_TRACE_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_TRACE_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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trace->base = attach_address;
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}
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static void
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bfin_trace_finish (struct hw *me)
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{
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struct bfin_trace *trace;
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trace = HW_ZALLOC (me, struct bfin_trace);
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set_hw_data (me, trace);
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set_hw_io_read_buffer (me, bfin_trace_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_trace_io_write_buffer);
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attach_bfin_trace_regs (me, trace);
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}
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2011-03-15 20:55:11 +00:00
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const struct hw_descriptor dv_bfin_trace_descriptor[] =
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{
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2011-03-06 00:20:21 +00:00
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{"bfin_trace", bfin_trace_finish,},
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{NULL, NULL},
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};
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#define TRACE_STATE(cpu) DV_STATE_CACHED (cpu, trace)
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/* This is not re-entrant, but neither is the cpu state, so this shouldn't
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be a big deal ... */
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void bfin_trace_queue (SIM_CPU *cpu, bu32 src_pc, bu32 dst_pc, int hwloop)
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{
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struct bfin_trace *trace = TRACE_STATE (cpu);
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struct bfin_trace_entry *e;
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int len, ivg;
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/* Only queue if powered. */
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if (!(trace->tbufctl & TBUFPWR))
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return;
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/* Only queue if enabled. */
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if (!(trace->tbufctl & TBUFEN))
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return;
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/* Ignore hardware loops.
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XXX: This is what the hardware does, but an option to ignore
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could be useful for debugging ... */
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if (hwloop >= 0)
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return;
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/* Only queue if at right level. */
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ivg = cec_get_ivg (cpu);
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if (ivg == IVG_RST)
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/* XXX: This is what the hardware does, but an option to ignore
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could be useful for debugging ... */
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return;
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if (ivg <= IVG_EVX && (trace->tbufctl & TBUFOVF))
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/* XXX: This is what the hardware does, but an option to ignore
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could be useful for debugging ... just don't throw an
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exception when full and in EVT{0..3}. */
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return;
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/* Are we full ? */
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len = TBUF_LEN (trace);
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if (len == SIM_BFIN_TRACE_LEN)
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{
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if (trace->tbufctl & TBUFOVF)
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{
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cec_exception (cpu, VEC_OVFLOW);
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return;
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}
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/* Overwrite next entry. */
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++trace->bottom;
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}
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/* One level compression. */
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if (len >= 1 && (trace->tbufctl & TBUFCMPLP))
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{
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e = TBUF_LAST (trace);
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if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1))
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{
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/* Hardware sets LSB when level is compressed. */
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e->dst |= 1;
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return;
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}
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}
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/* Two level compression. */
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if (len >= 2 && (trace->tbufctl & TBUFCMPLP_DOUBLE))
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{
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e = TBUF_LAST_LAST (trace);
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if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1))
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{
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/* Hardware sets LSB when level is compressed. */
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e->src |= 1;
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return;
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}
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}
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e = TBUF_TOP (trace);
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e->dst = dst_pc;
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e->src = src_pc;
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++trace->top;
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}
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