1996-11-25 19:52:08 +00:00
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#include "config.h"
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#include <signal.h>
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#ifdef HAVE_UNISTD_H
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#include <unistd.h>
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#endif
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#include "mn10300_sim.h"
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#include "simops.h"
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#include "sys/syscall.h"
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#include "bfd.h"
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#include <errno.h>
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#include <sys/stat.h>
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#include <sys/times.h>
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#include <sys/time.h>
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enum op_types {
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OP_UNKNOWN,
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};
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#ifdef DEBUG
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static void trace_input PARAMS ((char *name, enum op_types type, int size));
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static void trace_output PARAMS ((enum op_types result));
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static int init_text_p = 0;
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static asection *text;
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static bfd_vma text_start;
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static bfd_vma text_end;
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extern bfd *exec_bfd;
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#ifndef SIZE_INSTRUCTION
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#define SIZE_INSTRUCTION 6
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#endif
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#ifndef SIZE_OPERANDS
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#define SIZE_OPERANDS 16
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#endif
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#ifndef SIZE_VALUES
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#define SIZE_VALUES 11
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#endif
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#ifndef SIZE_LOCATION
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#define SIZE_LOCATION 40
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#endif
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static void
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trace_input (name, type, size)
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char *name;
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enum op_types type;
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int size;
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{
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}
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static void
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trace_output (result)
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enum op_types result;
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{
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}
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#else
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#define trace_input(NAME, IN1, IN2)
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#define trace_output(RESULT)
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#endif
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1996-11-27 07:20:36 +00:00
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/* mov imm8, dn */
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1996-11-25 19:52:08 +00:00
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void OP_8000 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov dm, dn */
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1996-11-25 19:52:08 +00:00
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void OP_80 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov dm, an */
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1996-11-25 19:52:08 +00:00
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void OP_F1E0 ()
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{
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1996-12-02 07:38:10 +00:00
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State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov am, dn */
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1996-11-25 19:52:08 +00:00
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void OP_F1D0 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov imm8, an */
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1996-11-25 19:52:08 +00:00
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void OP_9000 ()
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{
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1996-12-02 19:35:55 +00:00
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State.regs[REG_A0 + ((insn & 0x300) >> 8)] = insn & 0xff;
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov am, an */
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1996-11-25 19:52:08 +00:00
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void OP_90 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 05:29:49 +00:00
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/* mov sp, an */
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1996-11-25 19:52:08 +00:00
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void OP_3C ()
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{
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1996-11-27 00:53:25 +00:00
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State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 05:29:49 +00:00
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/* mov am, sp */
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1996-11-25 19:52:08 +00:00
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void OP_F2F0 ()
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{
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1996-11-27 00:53:25 +00:00
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State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov psw, dn */
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1996-11-25 19:52:08 +00:00
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void OP_F2E4 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_D0 + (insn & 0x3)] = PSW;
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov dm, psw */
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1996-11-25 19:52:08 +00:00
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void OP_F2F3 ()
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{
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1996-11-27 07:20:36 +00:00
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PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov mdr, dn */
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1996-11-25 19:52:08 +00:00
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void OP_F2E0 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov dm, mdr */
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1996-11-25 19:52:08 +00:00
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void OP_F2F2 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 16:51:30 +00:00
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/* mov (am), dn */
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1996-11-25 19:52:08 +00:00
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void OP_70 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_D0 + ((insn & 0xc) >> 2)]
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= load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 16:51:30 +00:00
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/* mov (d8,am), dn */
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1996-11-25 19:52:08 +00:00
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void OP_F80000 ()
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{
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1996-11-27 16:51:30 +00:00
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State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 17:19:44 +00:00
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/* mov (d16,am), dn */
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1996-11-25 19:52:08 +00:00
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void OP_FA000000 ()
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{
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1996-11-27 17:19:44 +00:00
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ SEXT16 (insn & 0xffff)), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 17:56:10 +00:00
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/* mov (d32,am), dn */
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1996-11-25 19:52:08 +00:00
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void OP_FC000000 ()
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{
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1996-11-27 17:56:10 +00:00
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State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ ((insn & 0xffff) << 16) | extension), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov (d8,sp), dn */
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1996-11-25 19:52:08 +00:00
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void OP_5800 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_D0 + ((insn & 0x300) >> 8)]
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1996-11-27 17:19:44 +00:00
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= load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 17:19:44 +00:00
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/* mov (d16,sp), dn */
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1996-11-25 19:52:08 +00:00
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void OP_FAB40000 ()
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{
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1996-11-27 17:19:44 +00:00
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
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= load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 17:56:10 +00:00
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/* mov (d32,sp), dn */
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1996-11-25 19:52:08 +00:00
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void OP_FCB40000 ()
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{
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1996-11-27 17:56:10 +00:00
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
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= load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 16:25:03 +00:00
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/* mov (di,am), dn */
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1996-11-25 19:52:08 +00:00
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void OP_F300 ()
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{
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1996-11-27 16:51:30 +00:00
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State.regs[REG_D0 + ((insn & 0x300) >> 8)]
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1996-11-27 16:25:03 +00:00
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= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
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+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov (abs16), dn */
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1996-11-25 19:52:08 +00:00
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void OP_300000 ()
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{
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1996-11-27 17:19:44 +00:00
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 17:56:10 +00:00
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/* mov (abs32), dn */
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1996-11-25 19:52:08 +00:00
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void OP_FCA40000 ()
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{
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1996-11-27 17:56:10 +00:00
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State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
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= load_mem ((((insn & 0xffff) << 16) + extension), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov (am), an */
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1996-11-25 19:52:08 +00:00
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void OP_F000 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_A0 + ((insn & 0xc) >> 2)]
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= load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 16:51:30 +00:00
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/* mov (d8,am), an */
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1996-11-25 19:52:08 +00:00
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void OP_F82000 ()
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{
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1996-11-27 16:51:30 +00:00
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State.regs[REG_A0 + ((insn & 0xc00) >> 10)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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+ SEXT8 (insn & 0xff)), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 17:19:44 +00:00
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/* mov (d16,am), an */
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1996-11-25 19:52:08 +00:00
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void OP_FA200000 ()
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{
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1996-11-27 17:19:44 +00:00
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State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ SEXT16 (insn & 0xffff)), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 17:56:10 +00:00
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/* mov (d32,am), an */
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1996-11-25 19:52:08 +00:00
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void OP_FC200000 ()
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{
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1996-11-27 17:56:10 +00:00
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State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
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= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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+ ((insn & 0xffff) << 16) + extension), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 07:20:36 +00:00
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/* mov (d8,sp), an */
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1996-11-25 19:52:08 +00:00
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void OP_5C00 ()
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{
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1996-11-27 07:20:36 +00:00
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State.regs[REG_A0 + ((insn & 0x300) >> 8)]
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1996-11-27 17:19:44 +00:00
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= load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 17:19:44 +00:00
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/* mov (d16,sp), an */
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1996-11-25 19:52:08 +00:00
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void OP_FAB00000 ()
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{
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1996-11-27 17:19:44 +00:00
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State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
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= load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
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1996-11-25 19:52:08 +00:00
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}
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1996-11-27 17:56:10 +00:00
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/* mov (d32,sp), an */
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1996-11-25 19:52:08 +00:00
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void OP_FCB00000 ()
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{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
= load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov (di,am), an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F380 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0x300) >> 8)]
|
1996-11-27 16:25:03 +00:00
|
|
|
|
= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
|
|
|
|
|
+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* mov (abs16), an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAA00000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov (abs32), an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCA00000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
= load_mem ((((insn & 0xffff) << 16) + extension), 4);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* mov (d8,am), sp */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8F000 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_SP]
|
|
|
|
|
= load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
|
|
|
|
|
+ SEXT8 (insn & 0xff)), 4);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* mov dm, (an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_60 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* mov dm, (d8,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F81000 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
|
|
|
|
|
+ SEXT8 (insn & 0xff)), 4,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* mov dm (d16,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA100000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ SEXT16 (insn & 0xffff)), 4,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov dm (d32,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC100000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ ((insn & 0xffff) << 16) + extension), 4,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* mov dm, (d8,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_4200 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
|
1996-11-27 07:20:36 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* mov dm, (d16,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA910000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov dm, (d32,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC910000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* mov dm, (di,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F340 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + (insn & 0x3)]
|
|
|
|
|
+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* mov dm, (abs16) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_10000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov dm, (abs32) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC810000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* mov am, (an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F010 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
|
|
|
|
|
State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* mov am, (d8,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F83000 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
|
|
|
|
|
+ SEXT8 (insn & 0xff)), 4,
|
|
|
|
|
State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov am, (d16,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA300000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
|
|
|
|
|
+ SEXT16 (insn & 0xffff)), 4,
|
|
|
|
|
State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov am, (d32,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC300000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
|
|
|
|
|
+ ((insn & 0xffff) << 16) + extension), 4,
|
|
|
|
|
State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* mov am, (d8,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_4300 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
|
1996-11-27 07:20:36 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* mov am, (d16,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA900000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
|
|
|
|
|
State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov am, (d32,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC900000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
|
|
|
|
|
State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* mov am, (di,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F3C0 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + (insn & 0x3)]
|
|
|
|
|
+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0x300) >> 8)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* mov am, (abs16) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA800000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov am, (abs32) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC800000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* mov sp, (d8,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8F400 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
store_mem (State.regs[REG_A0 + ((insn & 0x300) >> 8)] + SEXT8 (insn & 0xff),
|
|
|
|
|
4, State.regs[REG_SP]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* mov imm16, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_2C0000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned long value;
|
|
|
|
|
|
|
|
|
|
value = SEXT16 (insn & 0xffff);
|
1996-12-02 19:35:55 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov imm32,dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCCC0000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
unsigned long value;
|
|
|
|
|
|
|
|
|
|
value = (insn & 0xffff) << 16 | extension;
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* mov imm16, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_240000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned long value;
|
|
|
|
|
|
|
|
|
|
value = insn & 0xffff;
|
|
|
|
|
State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mov imm32, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCDC0000 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
unsigned long value;
|
|
|
|
|
|
|
|
|
|
value = (insn & 0xffff) << 16 | extension;
|
|
|
|
|
State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* movbu (am), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F040 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc) >> 2)]
|
|
|
|
|
= load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* movbu (d8,am), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F84000 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
|
|
|
|
|
= load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
|
|
|
|
|
+ SEXT8 (insn & 0xff)), 1);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* movbu (d16,am), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA400000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
|
|
|
|
|
= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ SEXT16 (insn & 0xffff)), 1);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movbu (d32,am), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC400000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
|
|
|
|
|
= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ ((insn & 0xffff) << 16) + extension), 1);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* movbu (d8,sp), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8B800 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)]
|
1996-11-27 17:19:44 +00:00
|
|
|
|
= load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* movbu (d16,sp), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAB80000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
= load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movbu (d32,sp), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCB80000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
= load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* movbu (di,am), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F400 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)]
|
1996-11-27 16:25:03 +00:00
|
|
|
|
= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
|
|
|
|
|
+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* movbu (abs16), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_340000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 1);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movbu (abs32), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCA80000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
= load_mem ((((insn & 0xffff) << 16) + extension), 1);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* movbu dm, (an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F050 ()
|
|
|
|
|
{
|
1996-12-02 07:38:10 +00:00
|
|
|
|
store_mem (State.regs[REG_A0 + (insn & 0x3)], 1,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* movbu dm, (d8,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F85000 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
|
|
|
|
|
+ SEXT8 (insn & 0xff)), 1,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* movbu dm, (d16,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA500000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
1996-11-27 17:56:10 +00:00
|
|
|
|
+ SEXT16 (insn & 0xffff)), 1,
|
1996-11-27 17:19:44 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movbu dm, (d32,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC500000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ ((insn & 0xffff) << 16) + extension), 1,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* movbu dm, (d8,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F89200 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* movbu dm, (d16,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA920000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movbu dm (d32,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC920000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* movbu dm, (di,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F440 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + (insn & 0x3)]
|
|
|
|
|
+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* movbu dm, (abs16) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_20000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movbu dm, (abs32) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC820000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* movhu (am), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F060 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc) >> 2)]
|
|
|
|
|
= load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* movhu (d8,am), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F86000 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
|
|
|
|
|
= load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
|
|
|
|
|
+ SEXT8 (insn & 0xff)), 2);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* movhu (d16,am), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA600000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
|
|
|
|
|
= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ SEXT16 (insn & 0xffff)), 2);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movhu (d32,am), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC600000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
|
|
|
|
|
= load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ ((insn & 0xffff) << 16) + extension), 2);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* movhu (d8,sp) dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8BC00 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)]
|
1996-11-27 17:19:44 +00:00
|
|
|
|
= load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* movhu (d16,sp), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FABC0000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
= load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movhu (d32,sp), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCBC0000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
= load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* movhu (di,am), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F480 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)]
|
1996-11-27 16:25:03 +00:00
|
|
|
|
= load_mem ((State.regs[REG_A0 + (insn & 0x3)]
|
|
|
|
|
+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* movhu (abs16), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_380000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 2);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movhu (abs32), dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCAC0000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
= load_mem ((((insn & 0xffff) << 16) + extension), 2);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* movhu dm, (an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F070 ()
|
|
|
|
|
{
|
1996-12-02 07:38:10 +00:00
|
|
|
|
store_mem (State.regs[REG_A0 + (insn & 0x3)], 2,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* movhu dm, (d8,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F87000 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
|
|
|
|
|
+ SEXT8 (insn & 0xff)), 2,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* movhu dm, (d16,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA700000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ SEXT16 (insn & 0xffff)), 2,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movhu dm, (d32,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC700000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ ((insn & 0xffff) << 16) + extension), 2,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* movhu dm,(d8,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F89300 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* movhu dm,(d16,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FA930000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movhu dm,(d32,sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC930000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* movhu dm, (di,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F4C0 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
store_mem ((State.regs[REG_A0 + (insn & 0x3)]
|
|
|
|
|
+ State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
|
1996-11-27 16:51:30 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* movhu dm, (abs16) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_30000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* movhu dm, (abs32) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FC830000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* ext dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F2D0 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
|
|
|
|
|
State.regs[REG_MDR] = -1;
|
|
|
|
|
else
|
|
|
|
|
State.regs[REG_MDR] = 0;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* extb dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_10 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* extbu dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_14 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* exth dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_18 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)]
|
|
|
|
|
= SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* exthu dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_1C ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 05:29:49 +00:00
|
|
|
|
/* movm (sp), reg_list */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_CE00 ()
|
|
|
|
|
{
|
1996-11-27 05:29:49 +00:00
|
|
|
|
unsigned long sp = State.regs[REG_SP];
|
|
|
|
|
unsigned long mask;
|
|
|
|
|
|
|
|
|
|
mask = insn & 0xff;
|
|
|
|
|
|
|
|
|
|
if (mask & 0x8)
|
|
|
|
|
{
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_LAR] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_LIR] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_MDR] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_A0 + 1] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_A0] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_D0 + 1] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_D0] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x10)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_A0 + 3] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x20)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_A0 + 2] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x40)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_D0 + 3] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x80)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_D0 + 2] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* And make sure to update the stack pointer. */
|
|
|
|
|
State.regs[REG_SP] = sp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* movm reg_list, (sp) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_CF00 ()
|
|
|
|
|
{
|
1996-11-27 05:29:49 +00:00
|
|
|
|
unsigned long sp = State.regs[REG_SP];
|
|
|
|
|
unsigned long mask;
|
|
|
|
|
|
|
|
|
|
mask = insn & 0xff;
|
|
|
|
|
|
|
|
|
|
if (mask & 0x80)
|
|
|
|
|
{
|
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_D0 + 2]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x40)
|
|
|
|
|
{
|
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_D0 + 3]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x20)
|
|
|
|
|
{
|
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_A0 + 2]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x10)
|
|
|
|
|
{
|
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_A0 + 3]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x8)
|
|
|
|
|
{
|
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_D0]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_D0 + 1]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_A0]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_A0 + 1]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_MDR]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_LIR]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
sp -= 4;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
store_mem (sp, 4, State.regs[REG_LAR]);
|
1996-11-27 05:29:49 +00:00
|
|
|
|
sp -= 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* And make sure to update the stack pointer. */
|
|
|
|
|
State.regs[REG_SP] = sp;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* clr dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_0 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
|
|
|
|
|
|
|
|
|
|
PSW |= PSW_Z;
|
|
|
|
|
PSW &= ~(PSW_V | PSW_C | PSW_N);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* add dm,dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_E0 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
value = reg1 + reg2;
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = value;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* add dm, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F160 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_A0 + (insn & 0x3)];
|
|
|
|
|
value = reg1 + reg2;
|
|
|
|
|
State.regs[REG_A0 + (insn & 0x3)] = value;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* add am, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F150 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
value = reg1 + reg2;
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = value;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* add am,an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F170 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_A0 + (insn & 0x3)];
|
|
|
|
|
value = reg1 + reg2;
|
|
|
|
|
State.regs[REG_A0 + (insn & 0x3)] = value;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* add imm8, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_2800 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-11-27 23:20:24 +00:00
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
|
1996-11-26 22:58:24 +00:00
|
|
|
|
imm = SEXT8 (insn & 0xff);
|
|
|
|
|
value = reg1 + imm;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)] = value;
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* add imm16, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAC00000 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-12-01 23:10:04 +00:00
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
|
1996-11-26 22:58:24 +00:00
|
|
|
|
imm = SEXT16 (insn & 0xffff);
|
|
|
|
|
value = reg1 + imm;
|
1996-12-01 23:10:04 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* add imm32,dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCC00000 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-12-01 23:10:04 +00:00
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
|
1996-11-26 22:58:24 +00:00
|
|
|
|
imm = ((insn & 0xffff) << 16) | extension;
|
|
|
|
|
value = reg1 + imm;
|
1996-12-01 23:10:04 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* add imm8, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_2000 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-11-27 23:20:24 +00:00
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
|
|
|
|
|
imm = SEXT8 (insn & 0xff);
|
1996-11-26 22:58:24 +00:00
|
|
|
|
value = reg1 + imm;
|
1996-11-27 23:20:24 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0x300) >> 8)] = value;
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* add imm16, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAD00000 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-12-01 23:10:04 +00:00
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
|
1996-11-27 23:20:24 +00:00
|
|
|
|
imm = SEXT16 (insn & 0xffff);
|
1996-11-26 22:58:24 +00:00
|
|
|
|
value = reg1 + imm;
|
1996-12-01 23:10:04 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* add imm32, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCD00000 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-12-01 23:10:04 +00:00
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
|
1996-11-26 22:58:24 +00:00
|
|
|
|
imm = ((insn & 0xffff) << 16) | extension;
|
|
|
|
|
value = reg1 + imm;
|
1996-12-01 23:10:04 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* add imm8, sp */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8FE00 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_SP];
|
|
|
|
|
imm = SEXT8 (insn & 0xff);
|
|
|
|
|
value = reg1 + imm;
|
|
|
|
|
State.regs[REG_SP] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* add imm16,sp */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAFE0000 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_SP];
|
|
|
|
|
imm = SEXT16 (insn & 0xffff);
|
|
|
|
|
value = reg1 + imm;
|
|
|
|
|
State.regs[REG_SP] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* add imm32, sp */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCFE0000 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_SP];
|
|
|
|
|
imm = ((insn & 0xffff) << 16) | extension;
|
|
|
|
|
value = reg1 + imm;
|
|
|
|
|
State.regs[REG_SP] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* addc dm,dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F140 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
value = reg1 + reg2 + ((PSW & PSW_C) != 0);
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = value;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* sub dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F100 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
value = reg2 - reg1;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
1996-12-02 20:12:08 +00:00
|
|
|
|
c = (reg1 > reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 07:20:36 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* sub dm, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F120 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_A0 + (insn & 0x3)];
|
|
|
|
|
value = reg2 - reg1;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
1996-12-02 20:12:08 +00:00
|
|
|
|
c = (reg1 > reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 07:20:36 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
|
|
|
|
State.regs[REG_A0 + (insn & 0x3)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* sub am, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F110 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
value = reg2 - reg1;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
1996-12-02 20:12:08 +00:00
|
|
|
|
c = (reg1 > reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 07:20:36 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* sub am, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F130 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_A0 + (insn & 0x3)];
|
|
|
|
|
value = reg2 - reg1;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
1996-12-02 20:12:08 +00:00
|
|
|
|
c = (reg1 > reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 07:20:36 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
|
|
|
|
State.regs[REG_A0 + (insn & 0x3)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* sub imm32, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCC40000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-12-04 00:42:01 +00:00
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
|
1996-11-27 07:20:36 +00:00
|
|
|
|
imm = ((insn & 0xffff) << 16) | extension;
|
|
|
|
|
value = reg1 - imm;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 07:20:36 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-12-04 00:42:01 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* sub imm32, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCD40000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-12-04 00:42:01 +00:00
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
|
1996-11-27 07:20:36 +00:00
|
|
|
|
imm = ((insn & 0xffff) << 16) | extension;
|
|
|
|
|
value = reg1 - imm;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 07:20:36 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-12-04 00:42:01 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* subc dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F180 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
value = reg2 - reg1 - ((PSW & PSW_C) != 0);
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
1996-12-02 20:12:08 +00:00
|
|
|
|
c = (reg1 > reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 07:20:36 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = value;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mul dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F240 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned long long temp;
|
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
temp = (State.regs[REG_D0 + (insn & 0x3)]
|
|
|
|
|
* State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
|
|
|
|
|
State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* mulu dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F250 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned long long temp;
|
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
temp = (State.regs[REG_D0 + (insn & 0x3)]
|
|
|
|
|
* State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
|
|
|
|
|
State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* div dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F260 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
long long temp;
|
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
temp = State.regs[REG_MDR];
|
|
|
|
|
temp <<= 32;
|
|
|
|
|
temp |= State.regs[REG_D0 + (insn & 0x3)];
|
1996-12-04 05:00:49 +00:00
|
|
|
|
State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
temp /= (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
1996-11-27 07:20:36 +00:00
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
|
|
|
|
|
State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* divu dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F270 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned long long temp;
|
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
temp = State.regs[REG_MDR];
|
|
|
|
|
temp <<= 32;
|
|
|
|
|
temp |= State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
|
|
|
|
|
State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* inc dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_40 ()
|
|
|
|
|
{
|
1996-12-04 18:02:00 +00:00
|
|
|
|
int z,n,c,v;
|
1996-12-06 05:30:24 +00:00
|
|
|
|
unsigned int value, imm, reg1;
|
1996-12-04 18:02:00 +00:00
|
|
|
|
|
1996-12-06 05:30:24 +00:00
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
imm = 1;
|
|
|
|
|
value = reg1 + imm;
|
1996-12-04 18:02:00 +00:00
|
|
|
|
State.regs[REG_D0 + ((insn & 0xc) >> 2)] = value;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
1996-12-06 05:30:24 +00:00
|
|
|
|
c = (reg1 < imm);
|
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-12-04 18:02:00 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* inc an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_41 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 00:53:25 +00:00
|
|
|
|
/* inc4 an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_50 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
State.regs[REG_A0 + (insn & 0x3)] += 4;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 00:53:25 +00:00
|
|
|
|
/* cmp imm8, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_A000 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
|
|
|
|
|
imm = SEXT8 (insn & 0xff);
|
|
|
|
|
value = reg1 - imm;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 00:53:25 +00:00
|
|
|
|
/* cmp dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_A0 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_D0 + (insn & 0x3)];
|
1996-11-27 07:20:36 +00:00
|
|
|
|
value = reg2 - reg1;
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
1996-12-02 20:12:08 +00:00
|
|
|
|
c = (reg1 > reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 00:53:25 +00:00
|
|
|
|
/* cmp dm, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F1A0 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_A0 + (insn & 0x3)];
|
1996-11-27 07:20:36 +00:00
|
|
|
|
value = reg2 - reg1;
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
1996-12-02 20:12:08 +00:00
|
|
|
|
c = (reg1 > reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 00:53:25 +00:00
|
|
|
|
/* cmp am, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F190 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_D0 + (insn & 0x3)];
|
1996-11-27 07:20:36 +00:00
|
|
|
|
value = reg2 - reg1;
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
1996-12-02 20:12:08 +00:00
|
|
|
|
c = (reg1 > reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 00:53:25 +00:00
|
|
|
|
/* cmp imm8, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_B000 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
|
|
|
|
|
imm = insn & 0xff;
|
|
|
|
|
value = reg1 - imm;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* cmp am, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_B0 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, reg2, value;
|
|
|
|
|
|
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
reg2 = State.regs[REG_A0 + (insn & 0x3)];
|
1996-11-27 07:20:36 +00:00
|
|
|
|
value = reg2 - reg1;
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
1996-12-02 20:12:08 +00:00
|
|
|
|
c = (reg1 > reg2);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
|
|
|
|
|
&& (reg2 & 0x80000000) != (value & 0x80000000));
|
1996-11-26 22:58:24 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* cmp imm16, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAC80000 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-12-04 00:42:01 +00:00
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
|
1996-11-27 00:53:25 +00:00
|
|
|
|
imm = SEXT16 (insn & 0xffff);
|
|
|
|
|
value = reg1 - imm;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* cmp imm32, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCC80000 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-12-04 00:42:01 +00:00
|
|
|
|
reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
|
1996-11-27 00:53:25 +00:00
|
|
|
|
imm = ((insn & 0xffff) << 16) | extension;
|
|
|
|
|
value = reg1 - imm;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* cmp imm16, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAD80000 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-12-04 00:42:01 +00:00
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
|
1996-11-27 00:53:25 +00:00
|
|
|
|
imm = insn & 0xffff;
|
|
|
|
|
value = reg1 - imm;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* cmp imm32, an */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCD80000 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
int z, c, n, v;
|
|
|
|
|
unsigned long reg1, imm, value;
|
|
|
|
|
|
1996-12-04 00:42:01 +00:00
|
|
|
|
reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
|
1996-11-27 00:53:25 +00:00
|
|
|
|
imm = ((insn & 0xffff) << 16) | extension;
|
|
|
|
|
value = reg1 - imm;
|
|
|
|
|
|
|
|
|
|
z = (value == 0);
|
|
|
|
|
n = (value & 0x80000000);
|
|
|
|
|
c = (reg1 < imm);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
v = ((reg1 & 0x80000000) != (imm & 0x80000000)
|
|
|
|
|
&& (reg1 & 0x80000000) != (value & 0x80000000));
|
1996-11-27 00:53:25 +00:00
|
|
|
|
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
|
|
|
|
|
| (c ? PSW_C : 0) | (v ? PSW_V : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* and dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F200 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* and imm8, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8E000 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)] &= (insn & 0xff);
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
|
1996-11-27 16:51:30 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* and imm16, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAE00000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)] &= (insn & 0xffff);
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
|
1996-11-27 17:19:44 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* and imm32, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCE00000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
&= ((insn & 0xffff) << 16 | extension);
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
|
1996-11-27 17:56:10 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* and imm16, psw */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAFC0000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
PSW &= (insn & 0xffff);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* or dm, dn*/
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F210 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* or imm8, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8E400 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)] |= insn & 0xff;
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
|
1996-11-27 16:51:30 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* or imm16, dn*/
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAE40000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)] |= insn & 0xffff;
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
|
1996-11-27 17:19:44 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* or imm32, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCE40000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
|= ((insn & 0xffff) << 16 | extension);
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
|
1996-11-27 17:56:10 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* or imm16,psw */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAFD0000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
PSW |= (insn & 0xffff);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* xor dm, dn*/
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F220 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* xor imm16, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAE80000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)] ^= insn & 0xffff;
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
|
1996-11-27 17:19:44 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* xor imm32, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCE80000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
^= ((insn & 0xffff) << 16 | extension);
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
|
1996-11-27 17:56:10 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* not dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F230 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* btst imm8, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8EC00 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int z, n;
|
|
|
|
|
|
|
|
|
|
temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
|
|
|
|
|
temp &= (insn & 0xff);
|
|
|
|
|
n = (temp & 0x80000000) != 0;
|
|
|
|
|
z = (temp == 0);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* btst imm16, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAEC0000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int z, n;
|
|
|
|
|
|
|
|
|
|
temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
|
|
|
|
|
temp &= (insn & 0xffff);
|
|
|
|
|
n = (temp & 0x80000000) != 0;
|
|
|
|
|
z = (temp == 0);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* btst imm32, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCEC0000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int z, n;
|
|
|
|
|
|
|
|
|
|
temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
|
|
|
|
|
temp &= ((insn & 0xffff) << 16 | extension);
|
|
|
|
|
n = (temp & 0x80000000) != 0;
|
|
|
|
|
z = (temp == 0);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* btst imm8,(abs32) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FE020000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
|
|
|
|
|
temp &= (extension & 0xff);
|
|
|
|
|
n = (temp & 0x80000000) != 0;
|
|
|
|
|
z = (temp == 0);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* btst imm8,(d8,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAF80000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ SEXT8 ((insn & 0xff00) >> 8)), 1);
|
|
|
|
|
temp &= (insn & 0xff);
|
|
|
|
|
n = (temp & 0x80000000) != 0;
|
|
|
|
|
z = (temp == 0);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* bset dm, (an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F080 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int z;
|
|
|
|
|
|
|
|
|
|
temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
|
|
|
|
|
z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
|
|
|
|
|
temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* bset imm8, (abs32) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FE000000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int z;
|
|
|
|
|
|
|
|
|
|
temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
|
|
|
|
|
z = (temp & (extension & 0xff)) == 0;
|
|
|
|
|
temp |= (extension & 0xff);
|
|
|
|
|
store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* bset imm8,(d8,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAF00000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int z;
|
|
|
|
|
|
|
|
|
|
temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ SEXT8 ((insn & 0xff00) >> 8)), 1);
|
|
|
|
|
z = (temp & (insn & 0xff)) == 0;
|
|
|
|
|
temp |= (insn & 0xff);
|
|
|
|
|
store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* bclr dm, (an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F090 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int z;
|
|
|
|
|
|
|
|
|
|
temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
|
|
|
|
|
z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
|
|
|
|
|
temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* bclr imm8, (abs32) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FE010000 ()
|
|
|
|
|
{
|
1996-11-27 17:56:10 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int z;
|
|
|
|
|
|
|
|
|
|
temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
|
|
|
|
|
z = (temp & (extension & 0xff)) == 0;
|
|
|
|
|
temp = ~temp & (extension & 0xff);
|
|
|
|
|
store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:19:44 +00:00
|
|
|
|
/* bclr imm8,(d8,an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAF40000 ()
|
|
|
|
|
{
|
1996-11-27 17:19:44 +00:00
|
|
|
|
unsigned long temp;
|
|
|
|
|
int z;
|
|
|
|
|
|
|
|
|
|
temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
|
|
|
|
|
+ SEXT8 ((insn & 0xff00) >> 8)), 1);
|
|
|
|
|
z = (temp & (insn & 0xff)) == 0;
|
|
|
|
|
temp = ~temp & (insn & 0xff);
|
|
|
|
|
store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
|
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= (z ? PSW_Z : 0);
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* asr dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F2B0 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
long temp;
|
|
|
|
|
int z, n, c;
|
|
|
|
|
|
|
|
|
|
temp = State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
c = temp & 1;
|
|
|
|
|
temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = temp;
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* asr imm8, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8C800 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
long temp;
|
|
|
|
|
int z, n, c;
|
|
|
|
|
|
|
|
|
|
temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
|
|
|
|
|
c = temp & 1;
|
|
|
|
|
temp >>= (insn & 0xff);
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)] = temp;
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
|
1996-11-27 16:51:30 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* lsr dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F2A0 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int z, n, c;
|
|
|
|
|
|
|
|
|
|
c = State.regs[REG_D0 + (insn & 0x3)] & 1;
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)]
|
|
|
|
|
>>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* lsr dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8C400 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
int z, n, c;
|
|
|
|
|
|
|
|
|
|
c = State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 1;
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)] >>= (insn & 0xff);
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] & 0x80000000) != 0;
|
1996-11-27 16:51:30 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* asl dm, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F290 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)]
|
|
|
|
|
<<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:51:30 +00:00
|
|
|
|
/* asl imm8, dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8C000 ()
|
|
|
|
|
{
|
1996-11-27 16:51:30 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + ((insn & 0x300) >> 8)] <<= (insn & 0xff);
|
|
|
|
|
z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
|
1996-11-27 16:51:30 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* asl2 dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_54 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
int n, z;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] <<= 2;
|
|
|
|
|
z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* ror dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F284 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned long value;
|
|
|
|
|
int c,n,z;
|
|
|
|
|
|
|
|
|
|
value = State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
if (value & 0x1)
|
|
|
|
|
c = 1;
|
|
|
|
|
|
|
|
|
|
value >>= 1;
|
|
|
|
|
value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = value;
|
|
|
|
|
z = (value == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (value & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* rol dn */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F280 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned long value;
|
|
|
|
|
int c,n,z;
|
|
|
|
|
|
|
|
|
|
value = State.regs[REG_D0 + (insn & 0x3)];
|
|
|
|
|
if (value & 0x80000000)
|
|
|
|
|
c = 1;
|
|
|
|
|
|
|
|
|
|
value <<= 1;
|
|
|
|
|
value |= ((PSW & PSW_C) != 0);
|
|
|
|
|
State.regs[REG_D0 + (insn & 0x3)] = value;
|
|
|
|
|
z = (value == 0);
|
1996-12-02 08:35:20 +00:00
|
|
|
|
n = (value & 0x80000000) != 0;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
|
|
|
|
|
PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* beq label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_C800 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (PSW & PSW_Z)
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bne label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_C900 ()
|
|
|
|
|
{
|
1996-11-26 22:58:24 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (!(PSW & PSW_Z))
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bgt label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_C100 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (!((PSW & PSW_Z)
|
|
|
|
|
|| (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bge label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_C200 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* ble label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_C300 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if ((PSW & PSW_Z)
|
|
|
|
|
|| (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* blt label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_C000 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bhi label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_C500 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bcc label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_C600 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (!(PSW & PSW_C))
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bls label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_C700 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bcs label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_C400 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (PSW & PSW_C)
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bvc label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8E800 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 3 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (!(PSW & PSW_V))
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 3;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bvs label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8E900 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 3 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (PSW & PSW_V)
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 3;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bnc label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8EA00 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 3 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (!(PSW & PSW_N))
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 3;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bns label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F8EB00 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 3 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
if (PSW & PSW_N)
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 3;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* bra label:8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_CA00 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
/* The dispatching code will add 2 after we return, so
|
|
|
|
|
we subtract two here to make things right. */
|
|
|
|
|
State.pc += SEXT8 (insn & 0xff) - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* leq */
|
|
|
|
|
void OP_D8 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* lne */
|
|
|
|
|
void OP_D9 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* lgt */
|
|
|
|
|
void OP_D1 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* lge */
|
|
|
|
|
void OP_D2 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* lle */
|
|
|
|
|
void OP_D3 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* llt */
|
|
|
|
|
void OP_D0 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* lhi */
|
|
|
|
|
void OP_D5 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* lcc */
|
|
|
|
|
void OP_D6 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* lls */
|
|
|
|
|
void OP_D7 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* lcs */
|
|
|
|
|
void OP_D4 ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* lra */
|
|
|
|
|
void OP_DA ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* setlb */
|
|
|
|
|
void OP_DB ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* jmp (an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F0F4 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* jmp label:16 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_CC0000 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
State.pc += SEXT16 (insn & 0xffff) - 3;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* jmp label:32 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_DC000000 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* call label:16,reg_list,imm8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_CD000000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned int next_pc, sp, adjust;
|
|
|
|
|
unsigned long mask;
|
|
|
|
|
|
|
|
|
|
sp = State.regs[REG_SP];
|
|
|
|
|
next_pc = State.pc + 2;
|
|
|
|
|
State.mem[sp] = next_pc & 0xff;
|
1996-11-27 18:36:54 +00:00
|
|
|
|
State.mem[sp+1] = (next_pc & 0xff00) >> 8;
|
|
|
|
|
State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
|
|
|
|
|
State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
|
|
|
|
|
mask = insn & 0xff;
|
|
|
|
|
|
|
|
|
|
adjust = 0;
|
|
|
|
|
if (mask & 0x80)
|
|
|
|
|
{
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x40)
|
|
|
|
|
{
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x20)
|
|
|
|
|
{
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x10)
|
|
|
|
|
{
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x8)
|
|
|
|
|
{
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_D0] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_A0] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_MDR] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_LIR] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_LAR] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* And make sure to update the stack pointer. */
|
|
|
|
|
State.regs[REG_SP] -= extension;
|
|
|
|
|
State.regs[REG_MDR] = next_pc;
|
|
|
|
|
State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* call label:32,reg_list,imm8*/
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_DD000000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned int next_pc, sp, adjust;
|
|
|
|
|
unsigned long mask;
|
|
|
|
|
|
|
|
|
|
sp = State.regs[REG_SP];
|
|
|
|
|
next_pc = State.pc + 2;
|
|
|
|
|
State.mem[sp] = next_pc & 0xff;
|
1996-11-27 18:36:54 +00:00
|
|
|
|
State.mem[sp+1] = (next_pc & 0xff00) >> 8;
|
|
|
|
|
State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
|
|
|
|
|
State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
|
1996-11-27 07:20:36 +00:00
|
|
|
|
|
|
|
|
|
mask = (extension & 0xff00) >> 8;
|
|
|
|
|
|
|
|
|
|
adjust = 0;
|
|
|
|
|
if (mask & 0x80)
|
|
|
|
|
{
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x40)
|
|
|
|
|
{
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x20)
|
|
|
|
|
{
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x10)
|
|
|
|
|
{
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x8)
|
|
|
|
|
{
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_D0] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_A0] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_MDR] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_LIR] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
State.regs[REG_LAR] = load_mem (sp + adjust, 4);
|
|
|
|
|
adjust -= 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* And make sure to update the stack pointer. */
|
|
|
|
|
State.regs[REG_SP] -= (extension & 0xff);
|
|
|
|
|
State.regs[REG_MDR] = next_pc;
|
|
|
|
|
State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* calls (an) */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_F0F0 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
unsigned int next_pc, sp;
|
|
|
|
|
|
|
|
|
|
sp = State.regs[REG_SP];
|
|
|
|
|
next_pc = State.pc + 2;
|
|
|
|
|
State.mem[sp] = next_pc & 0xff;
|
1996-11-27 18:36:54 +00:00
|
|
|
|
State.mem[sp+1] = (next_pc & 0xff00) >> 8;
|
|
|
|
|
State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
|
|
|
|
|
State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
|
1996-11-27 00:53:25 +00:00
|
|
|
|
State.regs[REG_MDR] = next_pc;
|
|
|
|
|
State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* calls label:16 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FAFF0000 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
unsigned int next_pc, sp;
|
|
|
|
|
|
|
|
|
|
sp = State.regs[REG_SP];
|
|
|
|
|
next_pc = State.pc + 4;
|
|
|
|
|
State.mem[sp] = next_pc & 0xff;
|
1996-11-27 18:36:54 +00:00
|
|
|
|
State.mem[sp+1] = (next_pc & 0xff00) >> 8;
|
|
|
|
|
State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
|
|
|
|
|
State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
|
1996-11-27 00:53:25 +00:00
|
|
|
|
State.regs[REG_MDR] = next_pc;
|
|
|
|
|
State.pc += SEXT16 (insn & 0xffff) - 4;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* calls label:32 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_FCFF0000 ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
unsigned int next_pc, sp;
|
|
|
|
|
|
|
|
|
|
sp = State.regs[REG_SP];
|
|
|
|
|
next_pc = State.pc + 6;
|
|
|
|
|
State.mem[sp] = next_pc & 0xff;
|
1996-11-27 18:36:54 +00:00
|
|
|
|
State.mem[sp+1] = (next_pc & 0xff00) >> 8;
|
|
|
|
|
State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
|
|
|
|
|
State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
|
1996-11-27 00:53:25 +00:00
|
|
|
|
State.regs[REG_MDR] = next_pc;
|
|
|
|
|
State.pc += (((insn & 0xffff) << 16) | extension) - 6;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 17:56:10 +00:00
|
|
|
|
/* ret reg_list, imm8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_DF0000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned int sp;
|
|
|
|
|
unsigned long mask;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_SP] += insn & 0xff;
|
|
|
|
|
State.pc = State.regs[REG_MDR] - 3;
|
|
|
|
|
sp = State.regs[REG_SP];
|
|
|
|
|
|
|
|
|
|
mask = (insn & 0xff00) >> 8;
|
|
|
|
|
|
|
|
|
|
if (mask & 0x8)
|
|
|
|
|
{
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_LAR] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_LIR] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_MDR] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_A0 + 1] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_A0] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_D0 + 1] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_D0] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x10)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_A0 + 3] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x20)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_A0 + 2] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x40)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_D0 + 3] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x80)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_D0 + 2] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
1996-11-27 07:20:36 +00:00
|
|
|
|
/* retf reg_list,imm8 */
|
1996-11-25 19:52:08 +00:00
|
|
|
|
void OP_DE0000 ()
|
|
|
|
|
{
|
1996-11-27 07:20:36 +00:00
|
|
|
|
unsigned int sp;
|
|
|
|
|
unsigned long mask;
|
|
|
|
|
|
|
|
|
|
State.regs[REG_SP] += insn & 0xff;
|
|
|
|
|
State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
|
|
|
|
|
| (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
|
|
|
|
|
State.pc -= 3;
|
|
|
|
|
|
|
|
|
|
sp = State.regs[REG_SP];
|
|
|
|
|
|
|
|
|
|
mask = (insn & 0xff00) >> 8;
|
|
|
|
|
|
|
|
|
|
if (mask & 0x8)
|
|
|
|
|
{
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_LAR] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_LIR] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_MDR] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_A0 + 1] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_A0] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_D0 + 1] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
State.regs[REG_D0] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x10)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_A0 + 3] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x20)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_A0 + 2] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x40)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_D0 + 3] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (mask & 0x80)
|
|
|
|
|
{
|
|
|
|
|
State.regs[REG_D0 + 2] = load_mem (sp, 4);
|
|
|
|
|
sp += 4;
|
|
|
|
|
}
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* rets */
|
|
|
|
|
void OP_F0FC ()
|
|
|
|
|
{
|
1996-11-27 00:53:25 +00:00
|
|
|
|
unsigned int sp;
|
|
|
|
|
|
|
|
|
|
sp = State.regs[REG_SP];
|
|
|
|
|
State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
|
|
|
|
|
| (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
|
|
|
|
|
State.pc -= 2;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* rti */
|
|
|
|
|
void OP_F0FD ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* trap */
|
|
|
|
|
void OP_F0FE ()
|
|
|
|
|
{
|
1996-11-27 18:36:54 +00:00
|
|
|
|
/* We use this for simulated system calls; we may need to change
|
|
|
|
|
it to a reserved instruction if we conflict with uses at
|
|
|
|
|
Matsushita. */
|
|
|
|
|
int save_errno = errno;
|
|
|
|
|
errno = 0;
|
|
|
|
|
|
|
|
|
|
/* Registers passed to trap 0 */
|
|
|
|
|
|
|
|
|
|
/* Function number. */
|
|
|
|
|
#define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
|
|
|
|
|
|
|
|
|
|
/* Parameters. */
|
|
|
|
|
#define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
|
|
|
|
|
#define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
|
|
|
|
|
#define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
|
|
|
|
|
|
|
|
|
|
/* Registers set by trap 0 */
|
|
|
|
|
|
|
|
|
|
#define RETVAL State.regs[0] /* return value */
|
|
|
|
|
#define RETERR State.regs[1] /* return error code */
|
|
|
|
|
|
|
|
|
|
/* Turn a pointer in a register into a pointer into real memory. */
|
|
|
|
|
|
|
|
|
|
#define MEMPTR(x) (State.mem + x)
|
|
|
|
|
|
|
|
|
|
switch (FUNC)
|
|
|
|
|
{
|
|
|
|
|
#if !defined(__GO32__) && !defined(_WIN32)
|
|
|
|
|
case SYS_fork:
|
|
|
|
|
RETVAL = fork ();
|
|
|
|
|
break;
|
|
|
|
|
case SYS_execve:
|
|
|
|
|
RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
|
|
|
|
|
(char **)MEMPTR (PARM3));
|
|
|
|
|
break;
|
|
|
|
|
case SYS_execv:
|
|
|
|
|
RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
case SYS_read:
|
|
|
|
|
RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
|
|
|
|
|
MEMPTR (PARM2), PARM3);
|
|
|
|
|
break;
|
|
|
|
|
case SYS_write:
|
|
|
|
|
if (PARM1 == 1)
|
|
|
|
|
RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
|
|
|
|
|
MEMPTR (PARM2), PARM3);
|
|
|
|
|
else
|
|
|
|
|
RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
|
|
|
|
|
MEMPTR (PARM2), PARM3);
|
|
|
|
|
break;
|
|
|
|
|
case SYS_lseek:
|
|
|
|
|
RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
|
|
|
|
|
break;
|
|
|
|
|
case SYS_close:
|
|
|
|
|
RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
|
|
|
|
|
break;
|
|
|
|
|
case SYS_open:
|
|
|
|
|
RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
|
|
|
|
|
break;
|
|
|
|
|
case SYS_exit:
|
|
|
|
|
/* EXIT - caller can look in PARM1 to work out the
|
|
|
|
|
reason */
|
|
|
|
|
if (PARM1 == 0xdead || PARM1 == 0x1)
|
|
|
|
|
State.exception = SIGABRT;
|
|
|
|
|
else
|
|
|
|
|
State.exception = SIGQUIT;
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case SYS_stat: /* added at hmsi */
|
|
|
|
|
/* stat system call */
|
|
|
|
|
{
|
|
|
|
|
struct stat host_stat;
|
|
|
|
|
reg_t buf;
|
|
|
|
|
|
|
|
|
|
RETVAL = stat (MEMPTR (PARM1), &host_stat);
|
|
|
|
|
|
|
|
|
|
buf = PARM2;
|
|
|
|
|
|
|
|
|
|
/* Just wild-assed guesses. */
|
|
|
|
|
store_mem (buf, 2, host_stat.st_dev);
|
|
|
|
|
store_mem (buf + 2, 2, host_stat.st_ino);
|
|
|
|
|
store_mem (buf + 4, 4, host_stat.st_mode);
|
|
|
|
|
store_mem (buf + 8, 2, host_stat.st_nlink);
|
|
|
|
|
store_mem (buf + 10, 2, host_stat.st_uid);
|
|
|
|
|
store_mem (buf + 12, 2, host_stat.st_gid);
|
|
|
|
|
store_mem (buf + 14, 2, host_stat.st_rdev);
|
|
|
|
|
store_mem (buf + 16, 4, host_stat.st_size);
|
|
|
|
|
store_mem (buf + 20, 4, host_stat.st_atime);
|
|
|
|
|
store_mem (buf + 28, 4, host_stat.st_mtime);
|
|
|
|
|
store_mem (buf + 36, 4, host_stat.st_ctime);
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case SYS_chown:
|
|
|
|
|
RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
|
|
|
|
|
break;
|
|
|
|
|
case SYS_chmod:
|
|
|
|
|
RETVAL = chmod (MEMPTR (PARM1), PARM2);
|
|
|
|
|
break;
|
|
|
|
|
case SYS_time:
|
|
|
|
|
RETVAL = time (MEMPTR (PARM1));
|
|
|
|
|
break;
|
|
|
|
|
case SYS_times:
|
|
|
|
|
{
|
|
|
|
|
struct tms tms;
|
|
|
|
|
RETVAL = times (&tms);
|
|
|
|
|
store_mem (PARM1, 4, tms.tms_utime);
|
|
|
|
|
store_mem (PARM1 + 4, 4, tms.tms_stime);
|
|
|
|
|
store_mem (PARM1 + 8, 4, tms.tms_cutime);
|
|
|
|
|
store_mem (PARM1 + 12, 4, tms.tms_cstime);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case SYS_gettimeofday:
|
|
|
|
|
{
|
|
|
|
|
struct timeval t;
|
|
|
|
|
struct timezone tz;
|
|
|
|
|
RETVAL = gettimeofday (&t, &tz);
|
|
|
|
|
store_mem (PARM1, 4, t.tv_sec);
|
|
|
|
|
store_mem (PARM1 + 4, 4, t.tv_usec);
|
|
|
|
|
store_mem (PARM2, 4, tz.tz_minuteswest);
|
|
|
|
|
store_mem (PARM2 + 4, 4, tz.tz_dsttime);
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case SYS_utime:
|
|
|
|
|
/* Cast the second argument to void *, to avoid type mismatch
|
|
|
|
|
if a prototype is present. */
|
|
|
|
|
RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
abort ();
|
|
|
|
|
}
|
|
|
|
|
RETERR = errno;
|
|
|
|
|
errno = save_errno;
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* rtm */
|
|
|
|
|
void OP_F0FF ()
|
|
|
|
|
{
|
1996-11-27 16:25:03 +00:00
|
|
|
|
abort ();
|
1996-11-25 19:52:08 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* nop */
|
|
|
|
|
void OP_CB ()
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* putx */
|
|
|
|
|
void OP_F500 ()
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* getx */
|
|
|
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void OP_F6F0 ()
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{
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}
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/* mulq */
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void OP_F600 ()
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{
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}
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/* mulq */
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void OP_F90000 ()
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{
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}
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/* mulq */
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void OP_FB000000 ()
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{
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}
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/* mulq */
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void OP_FD000000 ()
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{
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}
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/* mulqu */
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void OP_F610 ()
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{
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}
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/* mulqu */
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void OP_F91400 ()
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{
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}
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/* mulqu */
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void OP_FB140000 ()
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{
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}
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/* mulqu */
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void OP_FD140000 ()
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{
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}
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/* sat16 */
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void OP_F640 ()
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{
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}
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/* sat24 */
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void OP_F650 ()
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{
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}
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/* bsch */
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void OP_F670 ()
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{
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}
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