295 lines
9.4 KiB
C
295 lines
9.4 KiB
C
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/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "armdefs.h"
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#include "armemu.h"
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/***************************************************************************\
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* Definitions for the emulator architecture *
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\***************************************************************************/
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void ARMul_EmulateInit(void) ;
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ARMul_State *ARMul_NewState(void) ;
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void ARMul_Reset(ARMul_State *state) ;
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ARMword ARMul_DoCycle(ARMul_State *state) ;
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unsigned ARMul_DoCoPro(ARMul_State *state) ;
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ARMword ARMul_DoProg(ARMul_State *state) ;
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ARMword ARMul_DoInstr(ARMul_State *state) ;
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void ARMul_Abort(ARMul_State *state, ARMword address) ;
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unsigned ARMul_MultTable[32] = {1,2,2,3,3,4,4,5,5,6,6,7,7,8,8,9,9,
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10,10,11,11,12,12,13,13,14,14,15,15,16,16,16} ;
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ARMword ARMul_ImmedTable[4096] ; /* immediate DP LHS values */
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char ARMul_BitList[256] ; /* number of bits in a byte table */
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/***************************************************************************\
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* Call this routine once to set up the emulator's tables. *
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\***************************************************************************/
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void ARMul_EmulateInit(void)
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{unsigned long i, j ;
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for (i = 0 ; i < 4096 ; i++) { /* the values of 12 bit dp rhs's */
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ARMul_ImmedTable[i] = ROTATER(i & 0xffL,(i >> 7L) & 0x1eL) ;
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}
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for (i = 0 ; i < 256 ; ARMul_BitList[i++] = 0 ) ; /* how many bits in LSM */
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for (j = 1 ; j < 256 ; j <<= 1)
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for (i = 0 ; i < 256 ; i++)
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if ((i & j) > 0 )
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ARMul_BitList[i]++ ;
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for (i = 0 ; i < 256 ; i++)
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ARMul_BitList[i] *= 4 ; /* you always need 4 times these values */
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}
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/***************************************************************************\
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* Returns a new instantiation of the ARMulator's state *
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\***************************************************************************/
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ARMul_State *ARMul_NewState(void)
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{ARMul_State *state ;
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unsigned i, j ;
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state = (ARMul_State *)malloc(sizeof(ARMul_State)) ;
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memset (state, 0, sizeof (ARMul_State));
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state->Emulate = RUN ;
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for (i = 0 ; i < 16 ; i++) {
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state->Reg[i] = 0 ;
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for (j = 0 ; j < 7 ; j++)
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state->RegBank[j][i] = 0 ;
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}
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for (i = 0 ; i < 7 ; i++)
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state->Spsr[i] = 0 ;
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state->Mode = 0 ;
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state->CallDebug = FALSE ;
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state->Debug = FALSE ;
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state->VectorCatch = 0 ;
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state->Aborted = FALSE ;
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state->Reseted = FALSE ;
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state->Inted = 3 ;
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state->LastInted = 3 ;
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state->MemDataPtr = NULL ;
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state->MemInPtr = NULL ;
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state->MemOutPtr = NULL ;
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state->MemSparePtr = NULL ;
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state->MemSize = 0 ;
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state->OSptr = NULL ;
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state->CommandLine = NULL ;
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state->EventSet = 0 ;
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state->Now = 0 ;
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state->EventPtr = (struct EventNode **)malloc((unsigned)EVENTLISTSIZE *
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sizeof(struct EventNode *)) ;
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for (i = 0 ; i < EVENTLISTSIZE ; i++)
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*(state->EventPtr + i) = NULL ;
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#ifdef ARM61
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state->prog32Sig = LOW ;
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state->data32Sig = LOW ;
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#else
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state->prog32Sig = HIGH ;
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state->data32Sig = HIGH ;
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#endif
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state->lateabtSig = LOW ;
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state->bigendSig = LOW ;
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ARMul_Reset(state) ;
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return(state) ;
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}
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/***************************************************************************\
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* Call this routine to set ARMulator to model a certain processor *
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\***************************************************************************/
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void ARMul_SelectProcessor(ARMul_State *state, unsigned processor) {
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if (processor & ARM_Fix26_Prop) {
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state->prog32Sig = LOW;
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state->data32Sig = LOW;
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}else{
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state->prog32Sig = HIGH;
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state->data32Sig = HIGH;
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}
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state->lateabtSig = LOW;
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}
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/***************************************************************************\
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* Call this routine to set up the initial machine state (or perform a RESET *
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\***************************************************************************/
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void ARMul_Reset(ARMul_State *state)
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{state->NextInstr = 0 ;
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if (state->prog32Sig) {
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state->Reg[15] = 0 ;
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state->Cpsr = INTBITS | SVC32MODE ;
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}
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else {
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state->Reg[15] = R15INTBITS | SVC26MODE ;
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state->Cpsr = INTBITS | SVC26MODE ;
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}
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ARMul_CPSRAltered(state) ;
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state->Bank = SVCBANK ;
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FLUSHPIPE ;
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state->EndCondition = 0 ;
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state->ErrorCode = 0 ;
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state->Exception = FALSE ;
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state->NresetSig = HIGH ;
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state->NfiqSig = HIGH ;
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state->NirqSig = HIGH ;
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state->NtransSig = (state->Mode & 3)?HIGH:LOW ;
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state->abortSig = LOW ;
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state->AbortAddr = 1 ;
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state->NumInstrs = 0 ;
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state->NumNcycles = 0 ;
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state->NumScycles = 0 ;
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state->NumIcycles = 0 ;
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state->NumCcycles = 0 ;
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state->NumFcycles = 0 ;
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#ifdef ASIM
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(void)ARMul_MemoryInit() ;
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ARMul_OSInit(state) ;
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#endif
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}
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/***************************************************************************\
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* Emulate the execution of an entire program. Start the correct emulator *
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* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
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* address of the last instruction that is executed. *
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\***************************************************************************/
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ARMword ARMul_DoProg(ARMul_State *state)
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{ARMword pc = 0 ;
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state->Emulate = RUN ;
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while (state->Emulate != STOP) {
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state->Emulate = RUN ;
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if (state->prog32Sig && ARMul_MODE32BIT)
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pc = ARMul_Emulate32(state) ;
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else
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pc = ARMul_Emulate26(state) ;
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}
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return(pc) ;
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}
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/***************************************************************************\
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* Emulate the execution of one instruction. Start the correct emulator *
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* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
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* address of the instruction that is executed. *
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\***************************************************************************/
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ARMword ARMul_DoInstr(ARMul_State *state)
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{ARMword pc = 0 ;
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state->Emulate = ONCE ;
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if (state->prog32Sig && ARMul_MODE32BIT)
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pc = ARMul_Emulate32(state) ;
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else
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pc = ARMul_Emulate26(state) ;
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return(pc) ;
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}
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/***************************************************************************\
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* This routine causes an Abort to occur, including selecting the correct *
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* mode, register bank, and the saving of registers. Call with the *
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* appropriate vector's memory address (0,4,8 ....) *
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\***************************************************************************/
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void ARMul_Abort(ARMul_State *state, ARMword vector)
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{ARMword temp ;
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state->Aborted = FALSE ;
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if (ARMul_OSException(state,vector,ARMul_GetPC(state)))
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return ;
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if (state->prog32Sig)
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if (ARMul_MODE26BIT)
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temp = R15PC ;
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else
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temp = state->Reg[15] ;
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else
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temp = R15PC | ECC | ER15INT | EMODE ;
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switch (vector) {
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case ARMul_ResetV : /* RESET */
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state->Spsr[SVCBANK] = CPSR ;
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SETABORT(INTBITS,state->prog32Sig?SVC32MODE:SVC26MODE) ;
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ARMul_CPSRAltered(state) ;
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state->Reg[14] = temp ;
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break ;
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case ARMul_UndefinedInstrV : /* Undefined Instruction */
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state->Spsr[state->prog32Sig?UNDEFBANK:SVCBANK] = CPSR ;
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SETABORT(IBIT,state->prog32Sig?UNDEF32MODE:SVC26MODE) ;
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ARMul_CPSRAltered(state) ;
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state->Reg[14] = temp - 4 ;
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break ;
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case ARMul_SWIV : /* Software Interrupt */
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state->Spsr[SVCBANK] = CPSR ;
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SETABORT(IBIT,state->prog32Sig?SVC32MODE:SVC26MODE) ;
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ARMul_CPSRAltered(state) ;
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state->Reg[14] = temp - 4 ;
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break ;
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case ARMul_PrefetchAbortV : /* Prefetch Abort */
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state->AbortAddr = 1 ;
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state->Spsr[state->prog32Sig?ABORTBANK:SVCBANK] = CPSR ;
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SETABORT(IBIT,state->prog32Sig?ABORT32MODE:SVC26MODE) ;
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ARMul_CPSRAltered(state) ;
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state->Reg[14] = temp - 4 ;
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break ;
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case ARMul_DataAbortV : /* Data Abort */
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state->Spsr[state->prog32Sig?ABORTBANK:SVCBANK] = CPSR ;
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SETABORT(IBIT,state->prog32Sig?ABORT32MODE:SVC26MODE) ;
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ARMul_CPSRAltered(state) ;
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state->Reg[14] = temp - 4 ; /* the PC must have been incremented */
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break ;
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case ARMul_AddrExceptnV : /* Address Exception */
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state->Spsr[SVCBANK] = CPSR ;
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SETABORT(IBIT,SVC26MODE) ;
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ARMul_CPSRAltered(state) ;
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state->Reg[14] = temp - 4 ;
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break ;
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case ARMul_IRQV : /* IRQ */
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state->Spsr[IRQBANK] = CPSR ;
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SETABORT(IBIT,state->prog32Sig?IRQ32MODE:IRQ26MODE) ;
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ARMul_CPSRAltered(state) ;
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state->Reg[14] = temp - 4 ;
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break ;
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case ARMul_FIQV : /* FIQ */
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state->Spsr[FIQBANK] = CPSR ;
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SETABORT(INTBITS,state->prog32Sig?FIQ32MODE:FIQ26MODE) ;
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ARMul_CPSRAltered(state) ;
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state->Reg[14] = temp - 4 ;
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break ;
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}
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if (ARMul_MODE32BIT)
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ARMul_SetR15(state,vector) ;
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else
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ARMul_SetR15(state,R15CCINTMODE | vector) ;
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}
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