69 lines
1.5 KiB
C
69 lines
1.5 KiB
C
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#define SET_WORD_MEM(x,y) {saved_state.mem[(x)>>1] = y;}
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#define SET_BYTE_MEM(x,y) {BYTE_MEM(x)=y;}
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#define WORD_MEM(x) (saved_state.mem[(x)>>1])
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#define BYTE_MEM(x) (*(((char *)(saved_state.mem))+((x)^HOST_IS_LITTLE_ENDIAN)))
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#define CCR 8
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#define PC 9
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#define CYCLES 10
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#define HCHECK 11
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#define TIER 12
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#define TCSR 13
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#define FRC 14
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#define OCRA 15
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#define OCRB 16
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#define TCR 17
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#define TOCR 18
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#define ICRA 19
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#define NREG 20
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struct state
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{
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unsigned short int reg[NREG];
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unsigned char *(bregp[16]);
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unsigned char *(bregp_NNNNxxxx[256]);
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unsigned char *(bregp_xxxxNNNN[256]);
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unsigned short int *(wregp_xNNNxxxx[256]);
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unsigned short int *(wregp_xxxxxNNN[256]);
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int exception;
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int ienable;
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unsigned short *mem;
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}
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saved_state;
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#define OCFA (1<<3)
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#define OCFB (1<<2)
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#define CCLRA (1<<0)
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/* TCR bits */
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#define OCIEA (1<<3)
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#define OCIEB (1<<2)
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#define OVIE (1<<1)
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#define OVF (1<<1)
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/* TOCR bits */
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#define OCRS (1<<4)
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#ifdef __GO32__
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#define HOST_IS_LITTLE_ENDIAN 1
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#else
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#define HOST_IS_LITTLE_ENDIAN 0
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#endif
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#define SAVE_INTERPRETER_STATE() \
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saved_state.reg[CYCLES] = cycles; \
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saved_state.reg[PC] = (pc - saved_state.mem) <<1; \
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saved_state.reg[CCR] = GET_CCR(); \
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store_timer_state_to_mem();
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#define LOAD_INTERPRETER_STATE() \
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SET_CCR (saved_state.reg[CCR]); \
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checkfreq = saved_state.reg[HCHECK]; \
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pc = (saved_state.reg[PC]>>1) + saved_state.mem; \
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load_timer_state_from_mem(); \
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cycles=saved_state.reg[CYCLES];
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