arc/opcodes: Use flag operand class to handle multiple flag matches
When parsing the operand instruction flags we don't currently detect the
case where multiple flags are provided from the same class set, these
will be accepted and the bit values merged together, resulting in the
wrong instruction being assembled. For example:
adc.n.eq r0,r0,r2
Will assemble without error, yet, upon disassembly, the instruction will
actually be:
adc.c r0,r0,r2
In a later commit the concept of required flags will be introduced.
Required flags are just like normal instruction flags, except that they
must be present for the instruction to match. Adding this will allow
for simpler instructions in the instruction table, and allow for more
sharing of operand extraction and insertion functions.
To solve both of the above issues (multiple flags being invalid, and
required flags), this commit reworks the flag class mechanism.
Currently the flag class is never used. Each instruction can reference
multiple flag classes, each flag class has a class type and a set of
flags. However, at present, the class type is never used. The current
values identify the type of instruction that the flag will be used in,
but this is not required information.
Instead, this commit discards the old flag classes, and introduces 3 new
classes. The first F_CLASS_NONE, is just a NULL marker value, and is
only used in the NULL marker flag class. The other two flag classes are
F_FLAG_OPTIONAL, and F_FLAG_REQUIRED.
The class F_FLAG_OPTIONAL has the property that at most one of the flags
in the flag set for that class must be present in the instruction. The
"at most" one means that no flags being present is fine.
The class F_FLAG_REQUIRED is not currently used, but will be soon. With
this class, exactly one of the flags from this class must be present in
the instruction. If the flag class contains a single flag, then of
course that flag must be present. However, if the flag class contained
two or more, then one, and only one of them must be present.
gas/ChangeLog:
* config/tc-arc.c (find_opcode_match): Move lnflg, and i
declarations to start of block. Reset code on all flags before
attempting to match them. Handle multiple hits on the same flag.
Handle flag class.
* testsuite/gas/arc/asm-errors.d: New file.
* testsuite/gas/arc/asm-errors.err: New file.
* testsuite/gas/arc/asm-errors.s: New file.
include/ChangeLog:
* opcode/arc.h (flag_class_t): Remove all old flag classes, add 3
new classes instead.
opcodes/ChangeLog:
* arc-opc.c (arc_flag_classes): Convert all flag classes to use
the new class enum values.
2016-03-14 22:17:47 +00:00
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2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-opc.c (arc_flag_classes): Convert all flag classes to use
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the new class enum values.
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2016-03-15 21:51:50 +00:00
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2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-dis.c (print_insn_arc): Handle nps400.
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2016-03-01 11:41:12 +00:00
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2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
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* arc-opc.c (BASE): Delete.
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2016-03-18 17:02:20 +00:00
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2016-03-18 Nick Clifton <nickc@redhat.com>
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PR target/19721
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* aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
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of MOV insn that aliases an ORR insn.
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2016-03-16 16:11:59 +00:00
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2016-03-16 Jiong Wang <jiong.wang@arm.com>
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* arm-dis.c (neon_opcodes): Support new FP16 instructions.
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2016-03-07 15:16:28 +00:00
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2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* mcore-opc.h: Add const qualifiers.
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* microblaze-opc.h (struct op_code_struct): Likewise.
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* sh-opc.h: Likewise.
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* tic4x-dis.c (tic4x_print_indirect): Likewise.
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(tic4x_print_op): Likewise.
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2016-03-01 22:28:07 +00:00
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2016-03-02 Alan Modra <amodra@gmail.com>
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2016-03-02 13:50:27 +00:00
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* or1k-desc.h: Regenerate.
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2016-03-01 22:28:07 +00:00
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* fr30-ibld.c: Regenerate.
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2016-03-02 02:11:01 +00:00
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* rl78-decode.c: Regenerate.
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2016-03-01 22:28:07 +00:00
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2016-03-01 10:52:24 +00:00
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2016-03-01 Nick Clifton <nickc@redhat.com>
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PR target/19747
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* rl78-dis.c (print_insn_rl78_common): Fix typo.
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2016-02-24 14:08:39 +00:00
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2016-02-24 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
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(print_insn_coprocessor): Support fp16 instructions.
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2016-02-24 13:55:30 +00:00
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2016-02-24 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
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vminnm, vrint(mpna).
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2016-02-24 13:48:59 +00:00
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2016-02-24 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (print_insn_coprocessor): Check co-processor number for
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cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
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2016-02-15 23:58:42 +00:00
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2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (print_insn): Parenthesize expression to prevent
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truncated addresses.
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(OP_J): Likewise.
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Add support for ARC instruction relaxation in the assembler.
gas/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* config/tc-arc.h (TC_FRAG_TYPE, TC_PCREL_ADJUST, MAX_INSN_ARGS)
(MAX_INSN_FLGS, MAX_FLAG_NAME_LENGHT, TC_GENERIC_RELAX_TABLE):
Define.
(arc_flags, arc_relax_type): New structure.
* config/tc-arc.c (FRAG_MAX_GROWTH, RELAX_TABLE_ENTRY)
(RELAX_TABLE_ENTRY_MAX): New define.
(relaxation_state, md_relax_table, arc_relaxable_insns)
(arc_num_relaxable_ins): New variable.
(rlx_operand_type, arc_rlx_types): New enums.
(arc_relaxable_ins): New structure.
(OPTION_RELAX): New option.
(arc_insn): New relax member.
(arc_flags): Remove.
(relax_insn_p): New function.
(apply_fixups): Likewise.
(relaxable_operand): Likewise.
(may_relax_expr): Likewise.
(relaxable_flag): Likewise.
(arc_pcrel_adjust): Likewise.
(md_estimate_size_before_relax): Implement.
(md_convert_frag): Likewise.
(md_parse_option): Handle new mrelax option.
(md_show_usage): Likewise.
(assemble_insn): Set relax member.
(emit_insn0): New function.
(emit_insn1): Likewise.
(emit_insn): Handle relaxation case.
* NEWS: Mention the new relaxation option.
* doc/c-arc.texi (ARC Options): Document new mrelax option.
gas/testsuite
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
* gas/arc/relax-avoid1.d: New file.
* gas/arc/relax-avoid1.s: Likewise.
* gas/arc/relax-avoid2.d: Likewise.
* gas/arc/relax-avoid2.s: Likewise.
* gas/arc/relax-avoid3.d: Likewise.
* gas/arc/relax-avoid3.s: Likewise.
* gas/arc/relax-b.d: Likewise.
* gas/arc/relax-b.s: Likewise.
include/opcode/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc.h (arc_opcode arc_relax_opcodes, arc_num_relax_opcodes):
Declare.
opcodes/
2016-01-26 Claudiu Zissulescu <claziss@synopsys.com>
Janek van Oirschot <jvanoirs@synopsys.com>
* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
variable.
2016-02-10 12:09:01 +00:00
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2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
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Janek van Oirschot <jvanoirs@synopsys.com>
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* arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
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variable.
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2016-02-04 09:55:10 +00:00
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2016-02-04 Nick Clifton <nickc@redhat.com>
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PR target/19561
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* msp430-dis.c (print_insn_msp430): Add a special case for
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decoding an RRC instruction with the ZC bit set in the extension
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word.
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opcodes/cgen: Rework calculation of shift when inserting fields
The calculation of the shift amount, used to insert fields into the
instruction buffer, is not correct when the following conditions are all
true:
- CGEN_INT_INSN_P is defined, and true.
- CGEN_INSN_LSB0_P is true
- Total instruction length is greater than the length of a single
instruction word (the instruction is made of multiple words)
- The word offset is non-zero (the field is outside the first word)
When the above conditions are all true, the calculated shift fails to
take account of the total instruction length.
After this commit the calculation of the shift amount is split into two
parts, first we calculate the shift required to get to BIT0 of the word
in which the field lives, then we calculate the shift required to place
the field within the instruction word.
The change in this commit only effects the CGEN_INT_INSN_P defined true
case, but changes the code for both CGEN_INSN_LSB0_P true, and false.
In the case of CGEN_INSN_LSB0_P being false, the code used to say:
shift = total_length - (word_offset + start + length);
Now it says:
shift_to_word = total_length - (word_offset + word_length);
shift_within_word = word_length - start - length;
shift = shift_to_word + shift_within_word;
From which we can see that in all cases the computed shift value should
be unchanged.
In the case of CGEN_INSN_LSB0_P being true, the code used to say:
shift = (word_offset + start + 1) - length;
Now it says:
shift_to_word = total_length - (word_offset + word_length);
shift_within_word = start + 1 - length;
shift = shift_to_word + shift_within_word;
In the case where 'total_length == word_length' AND 'word_offset ==
0' (which indicates an instruction of a single word), we see that the
computed shift value will be unchanged. However, when the total_length
and word_length are different, and the word_offset is non-zero then the
computed shift value will be different (and correct).
opcodes/ChangeLog:
* cgen-ibld.in (insert_normal): Rework calculation of shift.
* epiphany-ibld.c: Regenerate.
* fr30-ibld.c: Regenerate.
* frv-ibld.c: Regenerate.
* ip2k-ibld.c: Regenerate.
* iq2000-ibld.c: Regenerate.
* lm32-ibld.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32r-ibld.c: Regenerate.
* mep-ibld.c: Regenerate.
* mt-ibld.c: Regenerate.
* or1k-ibld.c: Regenerate.
* xc16x-ibld.c: Regenerate.
* xstormy16-ibld.c: Regenerate.
2016-01-31 00:41:12 +00:00
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2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* cgen-ibld.in (insert_normal): Rework calculation of shift.
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* epiphany-ibld.c: Regenerate.
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* fr30-ibld.c: Regenerate.
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* frv-ibld.c: Regenerate.
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* ip2k-ibld.c: Regenerate.
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* iq2000-ibld.c: Regenerate.
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* lm32-ibld.c: Regenerate.
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* m32c-ibld.c: Regenerate.
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* m32r-ibld.c: Regenerate.
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* mep-ibld.c: Regenerate.
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* mt-ibld.c: Regenerate.
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* or1k-ibld.c: Regenerate.
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* xc16x-ibld.c: Regenerate.
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* xstormy16-ibld.c: Regenerate.
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2016-02-01 18:21:37 +00:00
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2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
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* epiphany-dis.c: Regenerated from latest cpu files.
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2016-02-01 10:41:32 +00:00
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2016-02-01 Michael McConville <mmcco@mykolab.com>
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* cgen-dis.c (count_decodable_bits): Use unsigned value for mask
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test bit.
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2016-01-25 15:06:54 +00:00
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2016-01-25 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (mapping_symbol_for_insn): New function.
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(find_ifthen_state): Call mapping_symbol_for_insn().
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2016-01-20 14:25:46 +00:00
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2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-opc.c (operand_general_constraint_met_p): Check validity
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of MSR UAO immediate operand.
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MIPS: Remove remnants of 48-bit microMIPS instruction support
The POOL48A major opcode was defined in early revisions of the 64-bit
microMIPS ISA, has never been implemented, and was removed before the
64-bit microMIPS ISA specification[1] has been finalized.
This complements commit a6c7053929dd ("MIPS/opcodes: Remove microMIPS
48-bit LI instruction").
References:
[1] "MIPS Architecture for Programmers, Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 3.06, October 17, 2012, Table 6.2 "microMIPS64 Encoding of
Major Opcode Field", p. 578
gas/
* config/tc-mips.c (micromips_insn_length): Remove the mention
of 48-bit microMIPS instructions.
gdb/
* mips-tdep.c (mips_insn_size): Remove 48-bit microMIPS
instruction support.
(micromips_next_pc): Likewise.
(micromips_scan_prologue): Likewise.
(micromips_deal_with_atomic_sequence): Likewise.
(micromips_stack_frame_destroyed_p): Likewise.
(mips_breakpoint_from_pc): Likewise.
opcodes/
* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
instruction support.
2016-01-18 21:29:37 +00:00
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2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
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* mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
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instruction support.
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2016-01-17 01:50:55 +00:00
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2016-01-17 Alan Modra <amodra@gmail.com>
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* configure: Regenerate.
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2016-01-14 16:23:35 +00:00
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2016-01-14 Nick Clifton <nickc@redhat.com>
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* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
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instructions that can support stack pointer operations.
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* rl78-decode.c: Regenerate.
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* rl78-dis.c: Fix display of stack pointer in MOVW based
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instructions.
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2016-01-14 10:55:11 +00:00
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2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
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* aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
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testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
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erxtatus_el1 and erxaddr_el1.
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2016-01-12 16:35:30 +00:00
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2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
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* arm-dis.c (arm_opcodes): Add "esb".
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(thumb_opcodes): Likewise.
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2016-01-11 17:54:58 +00:00
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2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c <xscmpnedp>: Delete.
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<xvcmpnedp>: Likewise.
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<xvcmpnedp.>: Likewise.
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<xvcmpnesp>: Likewise.
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<xvcmpnesp.>: Likewise.
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2016-01-08 10:38:00 +00:00
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2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
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PR gas/13050
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* m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
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addition to ISA_A.
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2016-01-01 11:25:12 +00:00
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2016-01-01 Alan Modra <amodra@gmail.com>
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Update year range in copyright notice of all files.
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2016-01-01 10:44:31 +00:00
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For older changes see ChangeLog-2015
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Copyright (C) 2016 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved.
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Local Variables:
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mode: change-log
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left-margin: 8
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fill-column: 74
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version-control: never
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End:
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