1995-10-31 18:29:37 +00:00
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#
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# This file is part of the program psim.
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#
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# Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2 of the License, or
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# (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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#
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1996-07-23 15:42:42 +00:00
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cache:RA:RA::
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cache:RA:rA:signed_word *:(cpu_registers(processor)->gpr + RA)
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cache:RA:RA_BITMASK:unsigned32:(1 << RA)
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cache:RT:RT::
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cache:RT:rT:signed_word *:(cpu_registers(processor)->gpr + RT)
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cache:RT:RT_BITMASK:unsigned32:(1 << RT)
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1996-08-06 15:55:32 +00:00
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cache:RS:RS::
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1996-07-23 15:42:42 +00:00
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cache:RS:rS:signed_word *:(cpu_registers(processor)->gpr + RS)
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cache:RS:RS_BITMASK:unsigned32:(1 << RS)
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1996-08-06 15:55:32 +00:00
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cache:RB:RB::
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1996-07-23 15:42:42 +00:00
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cache:RB:rB:signed_word *:(cpu_registers(processor)->gpr + RB)
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cache:RB:RB_BITMASK:unsigned32:(1 << RB)
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compute:FRA:FRA::
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cache:FRA:frA:unsigned64 *:(cpu_registers(processor)->fpr + FRA)
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cache:FRA:FRA_BITMASK:unsigned32:(1 << FRA)
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compute:FRB:FRB::
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cache:FRB:frB:unsigned64 *:(cpu_registers(processor)->fpr + FRB)
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cache:FRB:FRB_BITMASK:unsigned32:(1 << FRB)
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compute:FRC:FRC::
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cache:FRC:frC:unsigned64 *:(cpu_registers(processor)->fpr + FRC)
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cache:FRC:FRC_BITMASK:unsigned32:(1 << FRC)
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compute:FRS:FRS::
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cache:FRS:frS:unsigned64 *:(cpu_registers(processor)->fpr + FRS)
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cache:FRS:FRS_BITMASK:unsigned32:(1 << FRS)
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compute:FRT:FRT::
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cache:FRT:frT:unsigned64 *:(cpu_registers(processor)->fpr + FRT)
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cache:FRT:FRT_BITMASK:unsigned32:(1 << FRT)
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cache:SI:EXTS_SI:unsigned_word:((signed_word)(signed16)instruction)
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compute:BI:BI::
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cache:BI:BIT32_BI::BIT32(BI)
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cache:BF:BF::
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cache:BF:BF_BITMASK:unsigned32:(1 << BF)
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compute:BA:BA::
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cache:BA:BIT32_BA::BIT32(BA)
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cache:BA:BA_BITMASK:unsigned32:(1 << BA)
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compute:BB:BB::
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cache:BB:BIT32_BB::BIT32(BB)
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cache:BB:BB_BITMASK:unsigned32:(1 << BB)
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cache:BT:BT::
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cache:BT:BT_BITMASK:unsigned32:(1 << BT)
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cache:BD:EXTS_BD_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~3)
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cache:LI:EXTS_LI_0b00:unsigned_word:((((signed_word)(signed32)(instruction << 6)) >> 6) & ~0x3)
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cache:D:EXTS_D:unsigned_word:((signed_word)(signed16)(instruction))
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cache:DS:EXTS_DS_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~0x3)
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