223 lines
6.8 KiB
Text
223 lines
6.8 KiB
Text
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; OpenRISC 1000 architecture. -*- Scheme -*-
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; Copyright 2000-2014 Free Software Foundation, Inc.
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; Contributed by Peter Gavin, pgavin@gmail.com
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 3 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, see <http://www.gnu.org/licenses/>
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; Initial ORFPX32 instruction set
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; I'm not sure how CGEN handles rounding in FP operations, except for
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; in conversions to/from integers. So lf.add, lf.sub, lf.mul, and
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; lf.div do not round according to the FPCSR RM field.
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; NaN, overflow, and underflow are not yet handled either.
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(define-normal-insn-enum insn-opcode-float-regreg
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"floating point reg/reg insn opcode enums" ()
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OPC_FLOAT_REGREG_ f-op-7-8
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(("ADD_S" #x00)
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("SUB_S" #x01)
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("MUL_S" #x02)
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("DIV_S" #x03)
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("ITOF_S" #x04)
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("FTOI_S" #x05)
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("REM_S" #x06)
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("MADD_S" #x07)
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("SFEQ_S" #x08)
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("SFNE_S" #x09)
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("SFGT_S" #x0a)
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("SFGE_S" #x0b)
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("SFLT_S" #x0c)
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("SFLE_S" #x0d)
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("ADD_D" #x10)
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("SUB_D" #x11)
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("MUL_D" #x12)
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("DIV_D" #x13)
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("ITOF_D" #x14)
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("FTOI_D" #x15)
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("REM_D" #x16)
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("MADD_D" #x17)
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("SFEQ_D" #x18)
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("SFNE_D" #x19)
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("SFGT_D" #x1a)
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("SFGE_D" #x1b)
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("SFLT_D" #x1c)
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("SFLE_D" #x1d)
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("CUST1_S" #xd0)
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("CUST1_D" #xe0)
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)
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)
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(dnop rDSF "destination register (single floating point mode)" () h-fsr f-r1)
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(dnop rASF "source register A (single floating point mode)" () h-fsr f-r2)
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(dnop rBSF "source register B (single floating point mode)" () h-fsr f-r3)
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(dnop rDDF "destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
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(dnop rADF "source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
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(dnop rBDF "source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
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(define-pmacro (float-regreg-insn mnemonic)
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(begin
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(dni (.sym lf- mnemonic -s)
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(.str "lf." mnemonic ".s reg/reg/reg")
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((MACH ORFPX-MACHS))
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(.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF")
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(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S))
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(set SF rDSF (mnemonic SF rASF rBSF))
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()
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)
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(dni (.sym lf- mnemonic -d)
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(.str "lf." mnemonic ".d reg/reg/reg")
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((MACH ORFPX64-MACHS))
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(.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF")
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(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
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(set DF rDDF (mnemonic DF rADF rBDF))
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()
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)
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)
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)
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(float-regreg-insn add)
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(float-regreg-insn sub)
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(float-regreg-insn mul)
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(float-regreg-insn div)
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(dni lf-rem-s
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"lf.rem.s reg/reg/reg"
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((MACH ORFPX-MACHS))
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"lf.rem.s $rDSF,$rASF,$rBSF"
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(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S)
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(set SF rDSF (rem SF rASF rBSF))
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()
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)
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(dni lf-rem-d
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"lf.rem.d reg/reg/reg"
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((MACH ORFPX64-MACHS))
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"lf.rem.d $rDDF,$rADF,$rBDF"
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(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
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(set DF rDDF (mod DF rADF rBDF))
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()
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)
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(define-pmacro (get-rounding-mode)
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(case INT sys-fpcsr-rm
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((0) 1) ; TIES-TO-EVEN -- I'm assuming this is what is meant by "round to nearest"
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((1) 3) ; TOWARD-ZERO
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((2) 4) ; TOWARD-POSITIVE
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(else 5) ; TOWARD-NEGATIVE
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)
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)
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(dni lf-itof-s
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"lf.itof.s reg/reg"
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((MACH ORFPX-MACHS))
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"lf.itof.s $rDSF,$rA"
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(+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S)
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(set SF rDSF (float SF (get-rounding-mode) (trunc SI rA)))
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()
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)
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(dni lf-itof-d
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"lf.itof.d reg/reg"
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((MACH ORFPX64-MACHS))
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"lf.itof.d $rDSF,$rA"
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(+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
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(set DF rDDF (float DF (get-rounding-mode) rA))
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()
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)
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(dni lf-ftoi-s
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"lf.ftoi.s reg/reg"
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((MACH ORFPX-MACHS))
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"lf.ftoi.s $rD,$rASF"
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(+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S)
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(set WI rD (ext WI (fix SI (get-rounding-mode) rASF)))
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()
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)
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(dni lf-ftoi-d
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"lf.ftoi.d reg/reg"
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((MACH ORFPX64-MACHS))
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"lf.ftoi.d $rD,$rADF"
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(+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
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(set DI rD (fix DI (get-rounding-mode) rADF))
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()
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)
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(define-pmacro (float-setflag-insn mnemonic)
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(begin
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(dni (.sym lf- mnemonic -s)
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(.str "lf.sf" mnemonic ".s reg/reg")
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((MACH ORFPX-MACHS))
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(.str "lf.sf" mnemonic ".s $rASF,$rBSF")
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(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
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(set BI sys-sr-f (mnemonic SF rASF rBSF))
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()
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)
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(dni (.sym lf- mnemonic -d)
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(.str "lf.sf" mnemonic ".d reg/reg")
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((MACH ORFPX64-MACHS))
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(.str "lf.sf" mnemonic ".d $rASF,$rBSF")
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(+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
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(set BI sys-sr-f (mnemonic DF rADF rBDF))
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()
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)
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)
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)
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(float-setflag-insn eq)
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(float-setflag-insn ne)
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(float-setflag-insn ge)
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(float-setflag-insn gt)
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(float-setflag-insn lt)
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(float-setflag-insn le)
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(dni lf-madd-s
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"lf.madd.s reg/reg/reg"
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((MACH ORFPX-MACHS))
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"lf.madd.s $rDSF,$rASF,$rBSF"
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(+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S)
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(set SF rDSF (add SF (mul SF rASF rBSF) rDSF))
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()
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)
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(dni lf-madd-d
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"lf.madd.d reg/reg/reg"
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((MACH ORFPX64-MACHS))
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"lf.madd.d $rDDF,$rADF,$rBDF"
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(+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
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(set DF rDDF (add DF (mul DF rADF rBDF) rDDF))
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()
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)
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(define-pmacro (float-cust-insn cust-num)
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(begin
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(dni (.sym "lf-cust" cust-num "-s")
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(.str "lf.cust" cust-num ".s")
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((MACH ORFPX-MACHS))
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(.str "lf.cust" cust-num ".s $rASF,$rBSF")
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(+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S"))
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(nop)
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()
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)
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(dni (.sym "lf-cust" cust-num "-d")
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(.str "lf.cust" cust-num ".d")
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((MACH ORFPX64-MACHS))
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(.str "lf.cust" cust-num ".d")
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(+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
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(nop)
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()
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)
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)
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)
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(float-cust-insn "1")
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