315 lines
8.3 KiB
C
315 lines
8.3 KiB
C
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/* Target-dependent code for the SPARC 64 for GDB, the GNU debugger.
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Copyright 1986, 1987, 1989, 1991, 1992, 1993 Free Software Foundation, Inc.
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Contributed by Doug Evans (dje@cygnus.com).
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include "defs.h"
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#include "frame.h"
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#include "inferior.h"
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#include "obstack.h"
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#include "target.h"
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#include "ieee-float.h"
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/*#include "symfile.h" /* for objfiles.h */
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/*#include "objfiles.h" /* for find_pc_section */
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/* This file contains replacements and additions to sparc-tdep.c only.
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Some of this code has been written for a day when we can merge at least
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some of this with sparc-tdep.c. Macro TARGET_SPARC64 exists to allow some
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code to potentially be used by both. */
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#define TARGET_SPARC64 1 /* later make a config parm or some such */
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/* From infrun.c */
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extern int stop_after_trap;
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/* Branches with prediction are treated like their non-predicting cousins. */
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/* FIXME: What about floating point branches? */
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typedef enum
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{
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Error, not_branch, bicc, bicca, ba, baa, ticc, ta, done_retry
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} branch_type;
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/* Simulate single-step ptrace call for sun4. Code written by Gary
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Beihl (beihl@mcc.com). */
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/* npc4 and next_pc describe the situation at the time that the
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step-breakpoint was set, not necessary the current value of NPC_REGNUM. */
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static CORE_ADDR next_pc, npc4, target;
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static int brknpc4, brktrg;
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typedef char binsn_quantum[BREAKPOINT_MAX];
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static binsn_quantum break_mem[3];
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/* Non-zero if we just simulated a single-step ptrace call. This is
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needed because we cannot remove the breakpoints in the inferior
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process until after the `wait' in `wait_for_inferior'. Used for
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sun4. */
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int one_stepped;
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/* sparc64_single_step() is called just before we want to resume the inferior,
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if we want to single-step it but there is no hardware or kernel single-step
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support (as on all SPARCs). We find all the possible targets of the
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coming instruction and breakpoint them.
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single_step is also called just after the inferior stops. If we had
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set up a simulated single-step, we undo our damage. */
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/* FIXME: When the code is releasable, sparc's single step could become this
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one, removing the duplication. */
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void
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sparc64_single_step (ignore)
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int ignore; /* pid, but we don't need it */
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{
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branch_type br, isbranch();
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CORE_ADDR pc;
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long pc_instruction;
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if (!one_stepped)
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{
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/* Always set breakpoint for NPC. */
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next_pc = read_register (NPC_REGNUM);
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npc4 = next_pc + 4; /* branch not taken */
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target_insert_breakpoint (next_pc, break_mem[0]);
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/* printf ("set break at %x\n",next_pc); */
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pc = read_register (PC_REGNUM);
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pc_instruction = read_memory_integer (pc, sizeof(pc_instruction));
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br = isbranch (pc_instruction, pc, &target);
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brknpc4 = brktrg = 0;
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if (br == bicca)
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{
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/* Conditional annulled branch will either end up at
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npc (if taken) or at npc+4 (if not taken).
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Trap npc+4. */
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brknpc4 = 1;
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target_insert_breakpoint (npc4, break_mem[1]);
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}
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else if ((br == baa && target != next_pc)
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|| (TARGET_SPARC64 && br == done_retry))
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{
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/* Unconditional annulled branch will always end up at
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the target. */
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brktrg = 1;
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target_insert_breakpoint (target, break_mem[2]);
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}
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/* We are ready to let it go */
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one_stepped = 1;
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return;
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}
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else
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{
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/* Remove breakpoints */
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target_remove_breakpoint (next_pc, break_mem[0]);
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if (brknpc4)
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target_remove_breakpoint (npc4, break_mem[1]);
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if (brktrg)
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target_remove_breakpoint (target, break_mem[2]);
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one_stepped = 0;
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}
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}
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/* FIXME: sparc64_frame_chain() is temporary. sparc_frame_chain() can
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be fixed to support both of us. */
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#define FRAME_SAVED_L0 0 /* Byte offset from SP */
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#define FRAME_SAVED_I0 (8*REGISTER_RAW_SIZE (0)) /* Byte offset from SP */
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CORE_ADDR
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sparc64_frame_chain (thisframe)
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FRAME thisframe;
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{
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REGISTER_TYPE retval;
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int err;
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CORE_ADDR addr;
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addr = thisframe->frame + FRAME_SAVED_I0 +
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REGISTER_RAW_SIZE (0) * (FP_REGNUM - I0_REGNUM);
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err = target_read_memory (addr, (char *) &retval, sizeof (REGISTER_TYPE));
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if (err)
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return 0;
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SWAP_TARGET_AND_HOST (&retval, sizeof (retval));
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return retval;
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}
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CORE_ADDR
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sparc64_extract_struct_value_address (regbuf)
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char regbuf[REGISTER_BYTES];
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{
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CORE_ADDR addr;
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/* FIXME: We assume a non-leaf function. */
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addr = read_register (I0_REGNUM);
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return addr;
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}
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/* Find the pc saved in frame FRAME. */
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/* FIXME: This function can be removed when sparc_frame_saved_pc
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handles us too. */
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CORE_ADDR
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sparc64_frame_saved_pc (frame)
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FRAME frame;
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{
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int err;
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REGISTER_TYPE retval;
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CORE_ADDR addr,prev_pc;
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if (get_current_frame () == frame) /* FIXME, debug check. Remove >=gdb-4.6 */
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{
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if (read_register (SP_REGNUM) != frame->bottom) abort();
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}
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addr = frame->bottom + FRAME_SAVED_I0 +
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REGISTER_RAW_SIZE (0) * (I7_REGNUM - I0_REGNUM);
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err = target_read_memory (addr, (char *) &retval, sizeof (REGISTER_TYPE));
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if (err)
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return 0;
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SWAP_TARGET_AND_HOST (&retval, sizeof (retval));
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/* CORE_ADDR isn't always the same size as REGISTER_TYPE, so convert. */
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prev_pc = (CORE_ADDR) retval;
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return PC_ADJUST (prev_pc);
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}
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/* Check instruction at ADDR to see if it is an annulled branch or other
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instruction whose npc isn't pc+4 (eg: trap, done, retry).
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All other instructions will go to NPC or will trap.
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Set *TARGET if we find a candidate branch; set to zero if not. */
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branch_type
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isbranch (instruction, addr, target)
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long instruction;
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CORE_ADDR addr, *target;
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{
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branch_type val = not_branch;
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long int offset; /* Must be signed for sign-extend. */
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union
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{
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unsigned long int code;
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struct
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{
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unsigned int op:2;
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unsigned int a:1;
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unsigned int cond:4;
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unsigned int op2:3;
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unsigned int disp22:22;
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} b;
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struct
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{
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unsigned int op:2;
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unsigned int a:1;
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unsigned int cond:4;
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unsigned int op2:3;
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unsigned int cc:2;
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unsigned int p:1;
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unsigned int disp19:19;
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} bp;
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struct
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{
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unsigned int op:2;
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unsigned int a:1;
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unsigned int zero:1;
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unsigned int rcond:3;
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unsigned int op2:3;
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unsigned int disp16hi:2;
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unsigned int p:1;
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unsigned int rs1:5;
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unsigned int disp16lo:14;
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} bpr;
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struct
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{
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unsigned int op:2;
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unsigned int fcn:5;
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unsigned int op3:6;
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unsigned int reserved:19;
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} dr;
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} insn;
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*target = 0;
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insn.code = instruction;
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if (insn.b.op == 0
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&& (insn.b.op2 == 1 || insn.b.op2 == 2 || insn.b.op2 ==3
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|| insn.b.op2 == 5 || insn.b.op2 == 6))
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{
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if (insn.b.cond == 8)
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val = insn.b.a ? baa : ba;
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else
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val = insn.b.a ? bicca : bicc;
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switch (insn.b.op2)
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{
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case 1: /* bpcc */
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offset = 4 * ((int) (insn.bp.disp19 << 13) >> 13);
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break;
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case 2: /* bicc */
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offset = 4 * ((int) (insn.b.disp22 << 10) >> 10);
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break;
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case 3: /* bpr */
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offset = 4 * ((int) ((insn.bpr.disp16hi << 10)
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|| (insn.bpr.disp16lo << 18)) >> 13);
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break;
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case 5: /* fbpfcc */
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offset = 4 * ((int) (insn.bp.disp19 << 13) >> 13);
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break;
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case 6: /* fbfcc */
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offset = 4 * ((int) (insn.b.disp22 << 10) >> 10);
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break;
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}
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*target = addr + offset;
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}
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else if (insn.dr.op == 2 && insn.dr.op3 == 62)
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{
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if (insn.dr.fcn == 0)
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{
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/* done */
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*target = read_register (TNPC_REGNUM);
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val = done_retry;
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}
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else if (insn.dr.fcn == 1)
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{
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/* retry */
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*target = read_register (TPC_REGNUM);
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val = done_retry;
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}
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}
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return val;
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}
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/* We try to support 32 bit and 64 bit pointers.
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We are called when the Shade target is selected by shadeif.c. */
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int target_ptr_bit = 64; /* default */
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void
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set_target_ptr_bit(ptr_bit)
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int ptr_bit;
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{
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target_ptr_bit = ptr_bit;
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}
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