old-cross-binutils/sim/tic80/ic

compute:Dest:Dest:
compute:Dest:rDest:signed_word *:(&(CPU)->reg[Dest])
#
compute:Source1:Source1:
compute:Source1:vSource1:signed_word:(GPR (Source1) + 0)
#compute:Source1:vSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1])
#
compute:Source2:Source2:
compute:Source2:vSource2:signed_word:(GPR (Source2) + 0)
#compute:Source2:vSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2])
#
compute:Source:Source:
compute:Source:vSource:signed_word:(GPR (Source) + 0)
#compute:Source:vSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source])
#
compute:IndOff:IndOff:
compute:IndOff:rIndOff:signed_word:(GPR (IndOff) + 0)
#compute:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff])
#
compute:Base:Base:
compute:Base:vBase:signed_word:(GPR (Base) + 0)
compute:Base:rBase:signed_word*:(&GPR (Base))
#compute:Base:vBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base])
#
compute:Link:Link:
compute:Link:rLink:signed_word*:(&(CPU)->reg[Link])
#
# Trap Number
compute:UTN:UTN:
compute:INDTR:INDTR:
compute:INDTR:UTN:unsigned_word:(INDTR == 0 ? 0 : (CPU)->reg[INDTR])
#
compute:A:A:
#
compute:SignedImmediate:SignedImmediate:
compute:SignedImmediate:vSource1:signed_word:SEXT (SignedImmediate, 14)
#
compute:UnsignedImmediate:UnsignedImmediate:
compute:UnsignedImmediate:vSource1:signed_word:UnsignedImmediate
#
compute:BITNUM:BITNUM:
compute:Code:Code:
compute:BITNUM:bitnum:int:(~BITNUM) & 0x1f

#
compute:SignedOffset:SignedOffset:
compute:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14)
#
compute:UCRN:UCRN:
compute:INDCR:INDCR:
compute:INDCR:UCRN:unsigned32:(GPR (INDCR) + 0)
#compute:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR])
TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a. 1997-04-22 17:46:07 +00:00			`compute:Dest:Dest:`
More Tic80 instructions. 1997-04-23 13:56:14 +00:00			`compute:Dest:rDest:signed_word *:(&(CPU)->reg[Dest])`
TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a. 1997-04-22 17:46:07 +00:00			`#`
			`compute:Source1:Source1:`
o Make tic80 insn file more `cache ready' o Have igen always zero r0 instead of constantly checking if the designated register is r0. 1997-05-16 03:27:40 +00:00			`compute:Source1:vSource1:signed_word:(GPR (Source1) + 0)`
			`#compute:Source1:vSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1])`
TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a. 1997-04-22 17:46:07 +00:00			`#`
			`compute:Source2:Source2:`
o Make tic80 insn file more `cache ready' o Have igen always zero r0 instead of constantly checking if the designated register is r0. 1997-05-16 03:27:40 +00:00			`compute:Source2:vSource2:signed_word:(GPR (Source2) + 0)`
			`#compute:Source2:vSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2])`
TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a. 1997-04-22 17:46:07 +00:00			`#`
			`compute:Source:Source:`
o Make tic80 insn file more `cache ready' o Have igen always zero r0 instead of constantly checking if the designated register is r0. 1997-05-16 03:27:40 +00:00			`compute:Source:vSource:signed_word:(GPR (Source) + 0)`
			`#compute:Source:vSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source])`
TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a. 1997-04-22 17:46:07 +00:00			`#`
			`compute:IndOff:IndOff:`
o Make tic80 insn file more `cache ready' o Have igen always zero r0 instead of constantly checking if the designated register is r0. 1997-05-16 03:27:40 +00:00			`compute:IndOff:rIndOff:signed_word:(GPR (IndOff) + 0)`
			`#compute:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff])`
More Tic80 instructions. 1997-04-23 13:56:14 +00:00			`#`
			`compute:Base:Base:`
o Make tic80 insn file more `cache ready' o Have igen always zero r0 instead of constantly checking if the designated register is r0. 1997-05-16 03:27:40 +00:00			`compute:Base:vBase:signed_word:(GPR (Base) + 0)`
* ic (rBase, rLink): Make the type a pointer. 1998-04-24 09:54:50 +00:00			`compute:Base:rBase:signed_word*:(&GPR (Base))`
o Make tic80 insn file more `cache ready' o Have igen always zero r0 instead of constantly checking if the designated register is r0. 1997-05-16 03:27:40 +00:00			`#compute:Base:vBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base])`
More Tic80 instructions. 1997-04-23 13:56:14 +00:00			`#`
			`compute:Link:Link:`
* ic (rBase, rLink): Make the type a pointer. 1998-04-24 09:54:50 +00:00			`compute:Link:rLink:signed_word*:(&(CPU)->reg[Link])`
TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a. 1997-04-22 17:46:07 +00:00			`#`
			`# Trap Number`
			`compute:UTN:UTN:`
			`compute:INDTR:INDTR:`
More Tic80 instructions. 1997-04-23 13:56:14 +00:00			`compute:INDTR:UTN:unsigned_word:(INDTR == 0 ? 0 : (CPU)->reg[INDTR])`
TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a. 1997-04-22 17:46:07 +00:00			`#`
			`compute:A:A:`
			`#`
More Tic80 instructions. 1997-04-23 13:56:14 +00:00			`compute:SignedImmediate:SignedImmediate:`
			`compute:SignedImmediate:vSource1:signed_word:SEXT (SignedImmediate, 14)`
			`#`
			`compute:UnsignedImmediate:UnsignedImmediate:`
			`compute:UnsignedImmediate:vSource1:signed_word:UnsignedImmediate`
			`#`
TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a. 1997-04-22 17:46:07 +00:00			`compute:BITNUM:BITNUM:`
More Tic80 instructions. 1997-04-23 13:56:14 +00:00			`compute:Code:Code:`
Add assembler information to igen input files. 1997-05-30 07:25:13 +00:00			`compute:BITNUM:bitnum:int:(~BITNUM) & 0x1f`

More Tic80 instructions. 1997-04-23 13:56:14 +00:00			`#`
			`compute:SignedOffset:SignedOffset:`
			`compute:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14)`
Numerous fixes. 1997-04-29 08:41:15 +00:00			`#`
			`compute:UCRN:UCRN:`
			`compute:INDCR:INDCR:`
o Make tic80 insn file more `cache ready' o Have igen always zero r0 instead of constantly checking if the designated register is r0. 1997-05-16 03:27:40 +00:00			`compute:INDCR:UCRN:unsigned32:(GPR (INDCR) + 0)`
			`#compute:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR])`