63 lines
2.2 KiB
ArmAsm
63 lines
2.2 KiB
ArmAsm
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.section .text.start
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.align 4
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b _start
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.word 0,0
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.global _start
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.extern main
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_start:
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mov sp, #0x28000000
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//Disable caches/mpu
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mrc p15, 0, r0, c1, c0, 0
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bic r0, #0x1000 //Disable instruction cache
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bic r0, #0x4 //Disable data cache
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bic r0, #0x1 //Disable MPU
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mcr p15, 0, r0, c1, c0, 0
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ldr r0, =0x33333333
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mcr p15, 0, r0, c5, c0, 2 //Write data access
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mcr p15, 0, r0, c5, c0, 3 //Write instruction access
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// Sets MPU permissions and cache settings
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ldr r0, =0xFFFF001D // ffff0000 32k | bootrom (unprotected part)
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ldr r1, =0x3000801B // fff00000 16k | dtcm
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ldr r2, =0x01FF801D // 01ff8000 32k | itcm
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ldr r3, =0x08000029 // 08000000 2M | arm9 mem (O3DS / N3DS)
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ldr r4, =0x10000029 // 10000000 2M | io mem (ARM9 / first 2MB)
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ldr r5, =0x20000037 // 20000000 256M | fcram (O3DS / N3DS)
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ldr r6, =0x1FF00027 // 1FF00000 1M | dsp / axi wram
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ldr r7, =0x1800002D // 18000000 8M | vram (+ 2MB)
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mov r8, #0x29
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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mcr p15, 0, r3, c6, c3, 0
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mcr p15, 0, r4, c6, c4, 0
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mcr p15, 0, r8, c3, c0, 0 // Write bufferable 0, 3, 5
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mcr p15, 0, r8, c2, c0, 0 // Data cacheable 0, 3, 5
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mcr p15, 0, r8, c2, c0, 1 // Inst cacheable 0, 3, 5
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// Enable dctm
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ldr r0, =0x3000800A // set dtcm
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mcr p15, 0, r0, c9, c1, 0 // set the dtcm Region Register
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// Enable caches
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mrc p15, 0, r0, c1, c0, 0 // read control register
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orr r0, r0, #(1<<18) // - itcm enable
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orr r0, r0, #(1<<16) // - dtcm enable
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//orr r0, r0, #(1<<12) // - instruction cache enable
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//orr r0, r0, #(1<<2) // - data cache enable
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orr r0, r0, #(1<<0) // - mpu enable
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mcr p15, 0, r0, c1, c0, 0 // write control register
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// Flush caches
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 // flush I-cache
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mcr p15, 0, r0, c7, c6, 0 // flush D-cache
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mcr p15, 0, r0, c7, c10, 4 // drain write buffer
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// Fixes mounting of SDMC
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ldr r0, =0x10000020
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mov r1, #0x340
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str r1, [r0]
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b init
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