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Adds interrupt controller class.

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This commit is contained in:
Felix Queißner 2016-05-05 19:29:52 +02:00
parent b31d9164d6
commit bae2c0a763
3 changed files with 46 additions and 13 deletions
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17
prototypes/base/include/pic.hpp Normal file
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@ -0,0 +1,17 @@
#pragma once
#include <inttypes.h>
class PIC
{
private:
uint16_t port;
public:
PIC(uint16_t port);
void initialize(uint16_t irqBase, uint16_t icw3, uint16_t icw4);
void maskInterrupts(uint8_t mask);
};
extern PIC masterPIC, slavePIC;

18
prototypes/base/src/idt.cpp
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@ -1,6 +1,7 @@
#include "idt.hpp" #include "idt.hpp"
#include "io.hpp" #include "io.hpp"
#include "console.hpp" #include "console.hpp"
#include "pic.hpp"
#define ISR(num) extern "C" void isr_##num(); #define ISR(num) extern "C" void isr_##num();
#define ISR_ERR(num) ISR(num) #define ISR_ERR(num) ISR(num)
@ -44,20 +45,11 @@ void IDT::initialize()
void IDT::setupPIC() void IDT::setupPIC()
{ {
outb(0x20, 0x11); masterPIC.initialize(0x20, 0x04, 0x01);
outb(0x21, 0x20); slavePIC.initialize(0x28, 0x02, 0x01);
outb(0x21, 0x04);
outb(0x21, 0x01);
// Slave-PIC masterPIC.maskInterrupts(0x00);
outb(0xa0, 0x11); slavePIC.maskInterrupts(0x00);
outb(0xa1, 0x28);
outb(0xa1, 0x02);
outb(0xa1, 0x01);
// Demask all interrupts
outb(0x20, 0x0);
outb(0xa0, 0x0);
} }
void IDT::dispatch(CpuState *cpu) void IDT::dispatch(CpuState *cpu)

24
prototypes/base/src/pic.cpp Normal file
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@ -0,0 +1,24 @@
#include "pic.hpp"
#include "io.hpp"
PIC masterPIC(0x20);
PIC slavePIC(0xA0);
PIC::PIC(uint16_t port) :
port(port)
{
}
void PIC::initialize(uint16_t irqBase, uint16_t icw3, uint16_t icw4)
{
outb(this->port + 0x00, 0x11);
outb(this->port + 0x01, irqBase);
outb(this->port + 0x02, icw3);
outb(this->port + 0x03, icw4);
}
void PIC::maskInterrupts(uint8_t mask)
{
outb(this->port + 0x01, mask);
}