132 lines
3.3 KiB
ArmAsm
132 lines
3.3 KiB
ArmAsm
.align 4
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.global _start
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.extern start
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.section .text.boot
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_start:
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mrs r0, cpsr
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orr r0, r0, #0x80
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msr cpsr_c, r0 //Disable IRQs
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/* //Flush instruction cache
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0
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//Use nintendos data cache flusher here, because I don't want to reverse it
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ldr r0, =0xFFFF0830
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blx r0
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//Disable caches and MPU
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mrc p15, 0, r0, c1, c0, 0 //read
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bic r0, r0, #(1<<12) //Disable instruction cache
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bic r0, r0, #(1<<2) //Disable data cache
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bic r0, r0, #(1<<0) //disable mpu
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mcr p15, 0, r0, c1, c0, 0 //write
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//clear caches again
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0
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ldr r0, =0xFFFF0830
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blx r0
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*/
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ldr sp, =kernel_stack //set stack
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//Set other stacks
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mrs r0, cpsr
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bic r2, r0, #0x1F
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mov r1, r2
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orr r1, #0b10001 //FIQ
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msr cpsr, r1
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ldr sp, =interrupt_stack
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mov r1, r2
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orr r1, #0b10010 //IRQ
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msr cpsr, r1
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ldr sp, =interrupt_stack
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mov r1, r2
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orr r1, #0b10111 //Abort
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msr cpsr, r1
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ldr sp, =exception_stack
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mov r1, r2
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orr r1, #0b11011 //Undefined
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msr cpsr, r1
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ldr sp, =exception_stack
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mov r1, r2
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orr r1, #0b10011 //SVC
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msr cpsr, r1
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ldr sp, =svc_stack
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orr r1, #0b11111 //SYS
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msr cpsr, r1
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ldr sp, =kernel_stack
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/*
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//Configure ITCM to…something
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mrc p15, 0, r0, c9, c1, 1
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bic r0, #0b111110
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orr r0, #0b100010
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mcr p15, 0, r0, c9, c1, 1
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//Configure DTCM to address 0x30000000
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mrc p15, 0, r0, c9, c1, 0
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bic r0, #0b111110
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orr r0, #0b001010
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ldr r1, =0xFFFFF000
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bic r0, r1
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ldr r1, =0x30000000
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orr r0, r1
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mcr p15, 0, r0, c9, c1, 0
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//Enable both
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #(1<<18)
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bic r0, r0, #(1<<17)
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orr r0, r0, #(1<<16)
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mcr p15, 0, r0, c1, c0, 0
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//Give RW permissions to all memory regions
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ldr r0, =0x33333333
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mcr p15, 0, r0, c5, c0, 2 //Write Data
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mcr p15, 0, r0, c5, c0, 3 //Write instructions
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//Set MPU and caching
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ldr r0, =0xFFFF001F // ffff0000 64k bootrom
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ldr r1, =0x3000001B // 30000000 16k dtcm
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ldr r2, =0x00000035 // 00000000 128M ITCM
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ldr r3, =0x08000029 // 08000000 2M arm9 mem
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ldr r4, =0x10000029 // 10000000 2M IO mem
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ldr r5, =0x20000037 // 20000000 256M fcram
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ldr r6, =0x1FF00027 // 1FF00000 1M DSP
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ldr r7, =0x1800002D // 18000000 8M VRAM
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mcr p15, 0, r0, c6, c0, 0
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mcr p15, 0, r1, c6, c1, 0
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mcr p15, 0, r2, c6, c2, 0
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mcr p15, 0, r3, c6, c3, 0
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mcr p15, 0, r4, c6, c4, 0
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mcr p15, 0, r5, c6, c5, 0
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mcr p15, 0, r6, c6, c6, 0
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mcr p15, 0, r7, c6, c7, 0
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mov r0, #0b10101001 // unprot | arm9 | fcram | VRAM
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mcr p15, 0, r0, c2, c0, 0 // Data cacheable
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mcr p15, 0, r0, c2, c0, 1 // Instruction cacheable
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mcr p15, 0, r0, c3, c0, 0 // Data bufferable
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// Enable MPU and caching
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mcr p15, 0, r0, c3, c0, 0
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orr r0, r0, #(1<<12)
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orr r0, r0, #(1<<2)
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orr r0, r0, #(1<<0)
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mcr p15, 0, r0, c1, c0, 0
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*/
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//Certain bootloaders put the interrupt vectors in ITCM.
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//We don't want to mess with ITCM, so we put it back
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mrc p15, 0, r0, c1, c0, 0
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orr r0, #(1<<13)
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mcr p15, 0, r0, c1, c0, 0
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//Start start
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blx start
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.section .bss
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.align 16
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.space 4096
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interrupt_stack:
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.space 4096
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exception_stack:
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.space 4096
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svc_stack:
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.space 16384
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kernel_stack:
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