added source code generation for interrupt handling
This commit is contained in:
Morten Delenk
parent
e41b942c38
commit
352e211fb0
10 changed files with 369 additions and 1 deletions
2
.gitignore
vendored
2
.gitignore
vendored
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@ -13,3 +13,5 @@ iso/kernel
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*.firm
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html/
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latex/
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int.s
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regs.h
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12
config.py
12
config.py
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@ -89,3 +89,15 @@ if "ENABLE_FRAMEBUFFER_UNICODE" in config:
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p.stdin.write(l.encode("UTF-8"))
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p.stdin.close()
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p.wait()
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print("Generating sourcecode…")
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int_handler = open("kernel/arch/"+config["ARCH"]+"/int.s","w")
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import os
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try:
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os.makedirs("kernel/arch/"+config["ARCH"]+"/include")
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except:
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pass
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reg_struct = open("kernel/arch/"+config["ARCH"]+"/include/regs.h","w")
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exec(open("kernel/arch/"+config["ARCH"]+"/sourcegen.py").read())
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int_handler.close()
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reg_struct.close()
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87
kernel/arch/arm/sourcegen.py
Normal file
87
kernel/arch/arm/sourcegen.py
Normal file
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@ -0,0 +1,87 @@
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int_handler.write(
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"""\
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.arm
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.fpu vfpv2
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.global branch_macro
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branch_macro:
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ldr pc, [pc, #-4] //Load the next word into PC
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.global data_abort
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data_abort:
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sub lr, #4
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push {r0-r12,lr}
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ldr r0, =0
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blx intr_common_handler
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pop {r0-r12,pc}
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.global fast_irq
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fast_irq:
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sub lr, #4
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push {r0-r12,lr}
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ldr r0, =1
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blx intr_common_handler
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pop {r0-r12,pc}
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.global normal_irq
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normal_irq:
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sub lr, #4
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push {r0-r12,lr}
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ldr r0, =2
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blx intr_common_handler
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pop {r0-r12,pc}
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.global prefetch_abort
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prefetch_abort:
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sub lr, #4
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push {r0-r12,lr}
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ldr r0, =3
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blx intr_common_handler
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pop {r0-r12,pc}
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.global svc_call
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svc_call:
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push {r0-r12,lr}
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ldr r0, =4
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blx intr_common_handler
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pop {r0-r12,pc}
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.global undefined_op
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undefined_op:
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push {r0-r12,lr}
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ldr r0, =5
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blx intr_common_handler
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pop {r0-r12,pc}
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.extern handleINT
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intr_common_handler:
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""")
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push_regs=[]
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pop_regs=[]
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if ("ENABLE_HARD" in config) and config["ENABLE_HARD"]:
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#Save the registers
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for i,j in enumerate(["fpsid","fpscr","fpexc"]):
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push_regs.append("fmrx r"+str(i+1)+", "+j)
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pop_regs.append("fmxr "+j+", r"+str(i+1))
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push_regs.append("push {r1,r2,r3,r4,r5}")
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pop_regs.append("pop {r1,r2,r3,r4,r5}")
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push_regs.append("vpush {d0-d15}")
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pop_regs.append("vpop {d0-d15}")
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push_regs.append("mov r1, sp")
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pop_regs.append("mov sp, r0")
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for opc in push_regs:
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int_handler.write(" "+opc+"\n")
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int_handler.write(" blx handleINT\n")
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for opc in reversed(pop_regs):
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int_handler.write(" "+opc+"\n")
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int_handler.write(" bx lr\n")
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int_handler.write(".global panic\n.extern panic2\npanic:\n push {r0-r12,lr}\n")
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for opc in push_regs:
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int_handler.write(" "+opc+"\n")
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int_handler.write(" b panic\n")
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reg_struct.write("#include <stdint.h>\nstruct cpu_state {\n")
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if ("ENABLE_HARD" in config) and config["ENABLE_HARD"]:
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for reg in ["fpsid","fpscr","fpexc"]:
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reg_struct.write(" uint32_t "+reg+";\n")
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for reg in ("d"+str(i) for i in range(16)):
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reg_struct.write(" double "+reg+";\n")
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for i in range(13):
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reg_struct.write(" uint32_t r"+str(i)+";\n")
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reg_struct.write(" uint32_t pc;\n};")
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73
kernel/arch/x86/sourcegen.py
Normal file
73
kernel/arch/x86/sourcegen.py
Normal file
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@ -0,0 +1,73 @@
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print("Writing interrupt stubs")
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int_handler.write(".macro intr_stub nr\n.global intr_stub_\\nr\n.align 16\nintr_stub_\\nr:\n pushl $0\n pushl $\\nr\n jmp intr_common_handler\n.endm\n.macro intr_stub_error_code nr\n.global intr_stub_\\nr\n.align 16\nintr_stub_\\nr:\n pushl $\\nr\n jmp intr_common_handler\n.endm\n")
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for i in range(256):
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if i in [8,10,11,12,13,14,17]:
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int_handler.write("intr_stub_error_code "+str(i)+"\n")
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else:
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int_handler.write("intr_stub "+str(i)+"\n")
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int_handler.write(".extern handleINT\n")
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int_handler.write("intr_common_handler:\n")
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int_handler.write(" cli\n")
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print("Generating register save/restore")
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all_regs_push=[]
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all_regs_pop=[]
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data_section=""
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for reg in ["ebp","edi","esi","edx","ecx","ebx","eax"]:
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all_regs_push.append("push %"+reg)
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all_regs_pop.append("pop %"+reg)
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if config["ENABLE_FPU"] and not config["ENABLE_SSE"]:
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data_section+="fsave_reg:\n .space 108\n"
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all_regs_push.append("fsave fsave_reg")
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all_regs_pop.append("frstor fsave_reg")
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all_regs_push.append("pushl $fsave_reg")
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if config["ENABLE_SSE"]:
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data_section+=".align 16\nfxsave_reg:\n .space 512"
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all_regs_push.append("fxsave fxsave_reg")
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all_regs_pop.append("fxrstor fxsave_reg")
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all_regs_push.append("pushl $fxsave_reg")
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print("Writing interrupt handler")
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for ins in all_regs_push:
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int_handler.write(" "+ins+"\n")
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int_handler.write(" push %esp\n call handleINT\n mov %eax, %esp\n")
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for ins in reversed(all_regs_pop):
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int_handler.write(" "+ins+"\n")
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int_handler.write(" add $8, %esp\n iret\n")
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print("Writing panic handler")
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int_handler.write(".global panic\n.extern panic2\npanic:\n")
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for ins in all_regs_push:
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int_handler.write(" "+ins+"\n")
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int_handler.write(" push %esp\n jmp panic2\n")
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int_handler.write(".section .data\n"+data_section)
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print("Generating cpu_state struct")
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reg_struct.write("#include <stdint.h>\n")
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if config["ENABLE_FPU"] and not config["ENABLE_SSE"]:
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reg_struct.write("struct fpu_state {\n")
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for reg in ["cwd","swd","twd","fip","fcs","foo","fos"]:
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reg_struct.write(" uint32_t "+reg+";\n")
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for reg in ("st"+str(i) for i in range(8)):
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reg_struct.write(" __float80 "+reg+";\n")
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reg_struct.write("}__attribute__((packed,aligned(16)));\n")
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if config["ENABLE_SSE"]:
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reg_struct.write("struct fpu_state {\n")
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for reg in ["cwd","swd","twd","fop"]:
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reg_struct.write(" uint16_t "+reg+";\n")
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for reg in ["fip","fcs","foo","fos","mxcsr","mxcsr_mask"]:
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reg_struct.write(" uint32_t "+reg+";\n")
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for reg in range(8):
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reg_struct.write(" __float80 st"+str(reg)+";\n")
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reg_struct.write(" char buf"+str(reg)+"[6];\n")
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for reg in range(16):
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reg_struct.write(" __float128 xmm"+str(reg)+";\n")
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reg_struct.write("}__attribute__((packed,aligned(16)));\n")
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reg_struct.write("struct cpu_state {\n")
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if config["ENABLE_FPU"]:
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reg_struct.write(" fpu_state *fpu;\n")
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for reg in ["eax","ebx","ecx","edx","esi","edi","ebp","intr","error","eip","cs","eflags","esp","ss"]:
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reg_struct.write(" uint32_t "+reg+";\n")
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reg_struct.write("}__attribute__((packed));")
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73
kernel/arch/x86_64/sourcegen.py
Normal file
73
kernel/arch/x86_64/sourcegen.py
Normal file
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@ -0,0 +1,73 @@
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print("Writing interrupt stubs")
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int_handler.write(".macro intr_stub nr\n.global intr_stub_\\nr\n.align 16\nintr_stub_\\nr:\n pushq $0\n pushq $\\nr\n jmp intr_common_handler\n.endm\n.macro intr_stub_error_code nr\n.global intr_stub_\\nr\n.align 16\nintr_stub_\\nr:\n pushq $\\nr\n jmp intr_common_handler\n.endm\n")
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for i in range(256):
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if i in [8,10,11,12,13,14,17]:
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int_handler.write("intr_stub_error_code "+str(i)+"\n")
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else:
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int_handler.write("intr_stub "+str(i)+"\n")
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int_handler.write(".extern handleINT\n")
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int_handler.write("intr_common_handler:\n")
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int_handler.write(" cli\n")
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print("Generating register save/restore")
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all_regs_push=[]
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all_regs_pop=[]
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data_section=""
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for reg in ["r15","r14","r13","r12","r11","r10","r9","r8","rbp","rdi","rsi","rdx","rcx","rbx","rax"]:
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all_regs_push.append("push %"+reg)
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all_regs_pop.append("pop %"+reg)
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if config["ENABLE_FPU"] and not config["ENABLE_SSE"]:
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data_section+="fsave_reg:\n .space 108\n"
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all_regs_push.append("fsave fsave_reg")
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all_regs_pop.append("frstor fsave_reg")
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all_regs_push.append("pushq $fsave_reg")
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if config["ENABLE_SSE"]:
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data_section+=".align 16\nfxsave_reg:\n .space 512"
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all_regs_push.append("fxsave fxsave_reg")
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all_regs_pop.append("fxrstor fxsave_reg")
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all_regs_push.append("pushq $fxsave_reg")
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print("Writing interrupt handler")
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for ins in all_regs_push:
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int_handler.write(" "+ins+"\n")
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int_handler.write(" mov %rsp, %rdi\n call handleINT\n mov %rax, %rsp\n")
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for ins in reversed(all_regs_pop):
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int_handler.write(" "+ins+"\n")
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int_handler.write(" add $8, %esp\n iret\n")
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print("Writing panic handler")
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int_handler.write(".global panic\n.extern panic2\npanic:\n")
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for ins in all_regs_push:
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int_handler.write(" "+ins+"\n")
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int_handler.write(" mov %rsp, %rdi\n jmp panic2\n")
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int_handler.write(".section .data\n"+data_section)
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print("Generating cpu_state struct")
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reg_struct.write("#include <stdint.h>\n")
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if config["ENABLE_FPU"] and not config["ENABLE_SSE"]:
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reg_struct.write("struct fpu_state {\n")
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for reg in ["cwd","swd","twd","fip","fcs","foo","fos"]:
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reg_struct.write(" uint32_t "+reg+";\n")
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for reg in ("st"+str(i) for i in range(8)):
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reg_struct.write(" __float80 "+reg+";\n")
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reg_struct.write("}__attribute__((packed,aligned(16)));\n")
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if config["ENABLE_SSE"]:
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reg_struct.write("struct fpu_state {\n")
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for reg in ["cwd","swd","twd","fop"]:
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reg_struct.write(" uint16_t "+reg+";\n")
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for reg in ["fip","fcs","foo","fos","mxcsr","mxcsr_mask"]:
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reg_struct.write(" uint32_t "+reg+";\n")
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for reg in range(8):
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reg_struct.write(" __float80 st"+str(reg)+";\n")
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reg_struct.write(" char buf"+str(reg)+"[6];\n")
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for reg in range(16):
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reg_struct.write(" __float128 xmm"+str(reg)+";\n")
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reg_struct.write("}__attribute__((packed,aligned(16)));\n")
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reg_struct.write("struct cpu_state {\n")
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if config["ENABLE_FPU"]:
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reg_struct.write(" fpu_state *fpu;\n")
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for reg in ["rax","rbx","rcx","rdx","rsi","rdi","rbp","r8","r9","r10","r11","r12","r13","r14","r15","intr","error","rip","cs","rflags","rsp","ss"]:
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reg_struct.write(" uint64_t "+reg+";\n")
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reg_struct.write("}__attribute__((packed));")
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@ -20,7 +20,8 @@ PICAfb::PICAfb() : Framebuffer(25, 30) {
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*((uint32_t *)0x10202A40) = 0x3F; // Bottom screen brightness
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*((uint32_t *)0x10202244) = 0x1023E;
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*((uint32_t *)0x10202A44) = 0x1023E;
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// TODO this code is ugly and copied right out of the arm9loaderhax git
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// find out what 90% of this does
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// Top screen
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*(volatile uint32_t *)0x10400400 = 0x000001c2;
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*(volatile uint32_t *)0x10400404 = 0x000000d1;
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82
kernel/hw/pc/8259/pic.cpp
Normal file
82
kernel/hw/pc/8259/pic.cpp
Normal file
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@ -0,0 +1,82 @@
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#include "pic.hpp"
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#include "../io.hpp"
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#define PIC1 0x20
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#define PIC2 0xA0
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#define PIC1_COMMAND PIC1
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#define PIC1_DATA (PIC1 + 1)
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#define PIC2_COMMAND PIC2
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#define PIC2_DATA (PIC2 + 1)
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#define PIC_EOI 0x20
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#define ICW1_ICW4 0x01
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#define ICW1_SINGLE 0x02
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#define ICW1_INTERVAL4 0x04
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#define ICW1_LEVEL 0x08
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#define ICW1_INIT 0x10
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#define ICW4_8086 0x01
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#define ICW4_AUTO 0x02
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#define ICW4_BUF_SLAVE 0x04
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#define ICW4_BUF_MASTER 0x0C
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#define ICW4_SFNM 0x10
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namespace PIC {
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auto sendEOI(bool slave) -> void {
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if (slave) { out<unsigned char>(PIC2_COMMAND, PIC_EOI); }
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out<unsigned char>(PIC1_COMMAND, PIC_EOI);
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}
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auto initPIC(int off1, int off2) -> void {
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uint8_t a1 = in<uint8_t>(PIC1_DATA);
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uint8_t a2 = in<uint8_t>(PIC2_DATA);
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out<uint8_t>(PIC1_COMMAND, ICW1_INIT + ICW1_ICW4);
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out<uint8_t>(PIC2_COMMAND, ICW1_INIT + ICW1_ICW4);
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out<uint8_t>(PIC1_DATA, off1);
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out<uint8_t>(PIC2_DATA, off2);
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out<uint8_t>(PIC1_DATA, 4); // Slave at 2
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out<uint8_t>(PIC2_DATA, 2); // Self at 2
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out<uint8_t>(PIC1_DATA, ICW4_8086);
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out<uint8_t>(PIC2_DATA, ICW4_8086);
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out(PIC1_DATA, a1);
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out(PIC2_DATA, a2);
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}
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auto disable() -> void {
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out<uint8_t>(PIC1_DATA, 0xFF);
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out<uint8_t>(PIC2_DATA, 0xFF);
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}
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auto mask(int no) -> void {
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if (no < 8) {
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out<uint8_t>(PIC1_DATA, in<uint8_t>(PIC1_DATA) | (1 << no));
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} else {
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no -= 8;
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out<uint8_t>(PIC2_DATA, in<uint8_t>(PIC2_DATA) | (1 << no));
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}
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}
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auto unmask(int no) -> void {
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if (no < 8) {
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out<uint8_t>(PIC1_DATA, in<uint8_t>(PIC1_DATA) & ~(1 << no));
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} else {
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no -= 8;
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out<uint8_t>(PIC2_DATA, in<uint8_t>(PIC2_DATA) & ~(1 << no));
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}
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}
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auto disableSlave() -> void { mask(2); }
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auto enableSlave() -> void { unmask(2); }
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auto isSpurious(bool slave) -> bool {
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if (slave) {
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out<uint8_t>(PIC2_COMMAND, 0x0B);
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io_wait();
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if (!(in<uint8_t>(PIC2_DATA) & 0x80)) {
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sendEOI(false);
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return true;
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} else {
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return false;
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}
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} else {
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out<uint8_t>(PIC1_COMMAND, 0x0B);
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io_wait();
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return (in<uint8_t>(PIC1_DATA) & 0x80) ? true : false;
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}
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}
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}
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15
kernel/hw/pc/8259/pic.hpp
Normal file
15
kernel/hw/pc/8259/pic.hpp
Normal file
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@ -0,0 +1,15 @@
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#pragma once
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#include <stdint.h>
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/**
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* Namespace contains function to control the Programmable Interrupt Controller
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*/
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namespace PIC {
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auto sendEOI(bool slave) -> void; ///< Signals the PIC that the interrupt has ended
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auto initPIC(int off1, int off2) -> void; ///< Initializes the pic/remaps it
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auto disable() -> void; ///< disables PIC completely
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auto maskIRQ(int no) -> void; ///< disables a single IRQ
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auto unmaskIRQ(int no) -> void; ///< reenables a single IRQ
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auto disableSlave() -> void; ///< disables IRQ2 and 8-15
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auto enableSlave() -> void; ///< reenables at least IRQ2
|
||||
auto isSpurious(bool slave) -> bool; ///< Return if this isn't an actual IRQ.
|
||||
}
|
||||
|
|
@ -6,3 +6,5 @@ if config["ENABLE_FRAMEBUFFER"]:
|
|||
add_driver(False, "vesafb")
|
||||
else:
|
||||
add_driver(False, "cgaterm")
|
||||
add_driver(False, "8259")
|
||||
add_driver(False, "idt")
|
||||
|
|
|
|||
21
kernel/hw/pc/io.hpp
Normal file
21
kernel/hw/pc/io.hpp
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
template <typename T>
|
||||
static void out(uint16_t port, T val) {
|
||||
if (sizeof(T) == 1)
|
||||
asm volatile("outb %0, %1" : : "a"(val), "Nd"(port));
|
||||
else if (sizeof(T) == 2)
|
||||
asm volatile("outw %0, %1" : : "a"(val), "Nd"(port));
|
||||
else if (sizeof(T) == 4)
|
||||
asm volatile("outl %0, %1" : : "a"(val), "Nd"(port));
|
||||
}
|
||||
template <typename T>
|
||||
static T in(uint16_t port) {
|
||||
T val = 0;
|
||||
if (sizeof(T) == 1)
|
||||
asm volatile("inb %1, %0" : "=a"(val) : "Nd"(port));
|
||||
else if (sizeof(T) == 2)
|
||||
asm volatile("inw %1, %0" : "=a"(val) : "Nd"(port));
|
||||
else if (sizeof(T) == 4)
|
||||
asm volatile("inl %1, %0" : "=a"(val) : "Nd"(port));
|
||||
return val;
|
||||
}
|
||||
static void io_wait() { out<unsigned char>(0x80, 0); }
|
||||
Loading…
Reference in a new issue