27 lines
1.2 KiB
ArmAsm
27 lines
1.2 KiB
ArmAsm
.include "macros.inc"
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.section .text, "ax" # 0x80006A00 - 0x80406260 ; 0x003FF860
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.global __DSP_debug_printf
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__DSP_debug_printf:
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/* 80047550 00043390 94 21 FF 90 */ stwu r1, -0x70(r1)
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/* 80047554 00043394 40 86 00 24 */ bne cr1, lbl_80047578
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/* 80047558 00043398 D8 21 00 28 */ stfd f1, 0x28(r1)
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/* 8004755C 0004339C D8 41 00 30 */ stfd f2, 0x30(r1)
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/* 80047560 000433A0 D8 61 00 38 */ stfd f3, 0x38(r1)
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/* 80047564 000433A4 D8 81 00 40 */ stfd f4, 0x40(r1)
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/* 80047568 000433A8 D8 A1 00 48 */ stfd f5, 0x48(r1)
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/* 8004756C 000433AC D8 C1 00 50 */ stfd f6, 0x50(r1)
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/* 80047570 000433B0 D8 E1 00 58 */ stfd f7, 0x58(r1)
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/* 80047574 000433B4 D9 01 00 60 */ stfd f8, 0x60(r1)
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.global lbl_80047578
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lbl_80047578:
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/* 80047578 000433B8 90 61 00 08 */ stw r3, 0x8(r1)
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/* 8004757C 000433BC 90 81 00 0C */ stw r4, 0xc(r1)
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/* 80047580 000433C0 90 A1 00 10 */ stw r5, 0x10(r1)
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/* 80047584 000433C4 90 C1 00 14 */ stw r6, 0x14(r1)
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/* 80047588 000433C8 90 E1 00 18 */ stw r7, 0x18(r1)
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/* 8004758C 000433CC 91 01 00 1C */ stw r8, 0x1c(r1)
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/* 80047590 000433D0 91 21 00 20 */ stw r9, 0x20(r1)
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/* 80047594 000433D4 91 41 00 24 */ stw r10, 0x24(r1)
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/* 80047598 000433D8 38 21 00 70 */ addi r1, r1, 0x70
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/* 8004759C 000433DC 4E 80 00 20 */ blr
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