.include "macros.inc" .section .text, "ax" # 0x80006A00 - 0x80406260 ; 0x003FF860 .global UtlistToArray__Q24nw4r2efFPCQ34nw4r2ut4ListPPvi UtlistToArray__Q24nw4r2efFPCQ34nw4r2ut4ListPPvi: /* 800B30B0 000AEEF0 94 21 FF E0 */ stwu r1, -0x20(r1) /* 800B30B4 000AEEF4 7C 08 02 A6 */ mflr r0 /* 800B30B8 000AEEF8 90 01 00 24 */ stw r0, 0x24(r1) /* 800B30BC 000AEEFC 93 E1 00 1C */ stw r31, 0x1c(r1) /* 800B30C0 000AEF00 3B E0 00 00 */ li r31, 0x0 /* 800B30C4 000AEF04 93 C1 00 18 */ stw r30, 0x18(r1) /* 800B30C8 000AEF08 7C BE 2B 78 */ mr r30, r5 /* 800B30CC 000AEF0C 93 A1 00 14 */ stw r29, 0x14(r1) /* 800B30D0 000AEF10 7C 9D 23 78 */ mr r29, r4 /* 800B30D4 000AEF14 38 80 00 00 */ li r4, 0x0 /* 800B30D8 000AEF18 93 81 00 10 */ stw r28, 0x10(r1) /* 800B30DC 000AEF1C 7C 7C 1B 78 */ mr r28, r3 /* 800B30E0 000AEF20 48 00 00 1C */ b lbl_800B30FC .global lbl_800B30E4 lbl_800B30E4: /* 800B30E4 000AEF24 57 E5 13 BA */ rlwinm r5, r31, 2, 14, 29 /* 800B30E8 000AEF28 3B FF 00 01 */ addi r31, r31, 0x1 /* 800B30EC 000AEF2C 57 E0 04 3E */ clrlwi r0, r31, 16 /* 800B30F0 000AEF30 7C 7D 29 2E */ stwx r3, r29, r5 /* 800B30F4 000AEF34 7C 00 F0 00 */ cmpw r0, r30 /* 800B30F8 000AEF38 40 80 00 18 */ bge lbl_800B3110 .global lbl_800B30FC lbl_800B30FC: /* 800B30FC 000AEF3C 7F 83 E3 78 */ mr r3, r28 /* 800B3100 000AEF40 4B FF 08 31 */ bl MEMGetNextListObject /* 800B3104 000AEF44 2C 03 00 00 */ cmpwi r3, 0x0 /* 800B3108 000AEF48 7C 64 1B 78 */ mr r4, r3 /* 800B310C 000AEF4C 40 82 FF D8 */ bne lbl_800B30E4 .global lbl_800B3110 lbl_800B3110: /* 800B3110 000AEF50 7F E3 FB 78 */ mr r3, r31 /* 800B3114 000AEF54 83 E1 00 1C */ lwz r31, 0x1c(r1) /* 800B3118 000AEF58 83 C1 00 18 */ lwz r30, 0x18(r1) /* 800B311C 000AEF5C 83 A1 00 14 */ lwz r29, 0x14(r1) /* 800B3120 000AEF60 83 81 00 10 */ lwz r28, 0x10(r1) /* 800B3124 000AEF64 80 01 00 24 */ lwz r0, 0x24(r1) /* 800B3128 000AEF68 7C 08 03 A6 */ mtlr r0 /* 800B312C 000AEF6C 38 21 00 20 */ addi r1, r1, 0x20 /* 800B3130 000AEF70 4E 80 00 20 */ blr /* 800B3134 000AEF74 00 00 00 00 */ .4byte 0x00000000 /* 800B3138 000AEF78 00 00 00 00 */ .4byte 0x00000000 /* 800B313C 000AEF7C 00 00 00 00 */ .4byte 0x00000000 .global GetDirMtxY__Q24nw4r2efFPQ34nw4r4math5MTX34RCQ34nw4r4math4VEC3 GetDirMtxY__Q24nw4r2efFPQ34nw4r4math5MTX34RCQ34nw4r4math4VEC3: /* 800B3140 000AEF80 94 21 FF D0 */ stwu r1, -0x30(r1) /* 800B3144 000AEF84 7C 08 02 A6 */ mflr r0 /* 800B3148 000AEF88 C1 02 8B 4C */ lfs f8, "@6743"@sda21(r2) /* 800B314C 000AEF8C 90 01 00 34 */ stw r0, 0x34(r1) /* 800B3150 000AEF90 C0 02 8B 50 */ lfs f0, "@6744"@sda21(r2) /* 800B3154 000AEF94 DB E1 00 20 */ stfd f31, 0x20(r1) /* 800B3158 000AEF98 F3 E1 00 28 */ psq_st f31, 0x28(r1), 0, qr0 /* 800B315C 000AEF9C C3 E4 00 08 */ lfs f31, 0x8(r4) /* 800B3160 000AEFA0 DB C1 00 10 */ stfd f30, 0x10(r1) /* 800B3164 000AEFA4 FC 20 FA 10 */ fabs f1, f31 /* 800B3168 000AEFA8 F3 C1 00 18 */ psq_st f30, 0x18(r1), 0, qr0 /* 800B316C 000AEFAC 93 E1 00 0C */ stw r31, 0xc(r1) /* 800B3170 000AEFB0 EC 28 08 28 */ fsubs f1, f8, f1 /* 800B3174 000AEFB4 7C 9F 23 78 */ mr r31, r4 /* 800B3178 000AEFB8 93 C1 00 08 */ stw r30, 0x8(r1) /* 800B317C 000AEFBC 7C 7E 1B 78 */ mr r30, r3 /* 800B3180 000AEFC0 FC 01 00 40 */ fcmpo cr0, f1, f0 /* 800B3184 000AEFC4 40 80 00 10 */ bge lbl_800B3194 /* 800B3188 000AEFC8 C0 C2 8B 54 */ lfs f6, "@6745"@sda21(r2) /* 800B318C 000AEFCC FC E0 30 90 */ fmr f7, f6 /* 800B3190 000AEFD0 48 00 00 40 */ b lbl_800B31D0 .global lbl_800B3194 lbl_800B3194: /* 800B3194 000AEFD4 EC 1F 07 F2 */ fmuls f0, f31, f31 /* 800B3198 000AEFD8 C0 C2 8B 54 */ lfs f6, "@6745"@sda21(r2) /* 800B319C 000AEFDC EF C8 00 28 */ fsubs f30, f8, f0 /* 800B31A0 000AEFE0 FC 1E 30 40 */ fcmpo cr0, f30, f6 /* 800B31A4 000AEFE4 4C 40 13 82 */ cror eq, lt, eq /* 800B31A8 000AEFE8 40 82 00 08 */ bne lbl_800B31B0 /* 800B31AC 000AEFEC 48 00 00 10 */ b lbl_800B31BC .global lbl_800B31B0 lbl_800B31B0: /* 800B31B0 000AEFF0 FC 20 F0 90 */ fmr f1, f30 /* 800B31B4 000AEFF4 48 04 B8 BD */ bl FrSqrt__Q24nw4r4mathFf /* 800B31B8 000AEFF8 EC DE 00 72 */ fmuls f6, f30, f1 .global lbl_800B31BC lbl_800B31BC: /* 800B31BC 000AEFFC FC 20 30 50 */ fneg f1, f6 /* 800B31C0 000AF000 C0 5F 00 04 */ lfs f2, 0x4(r31) /* 800B31C4 000AF004 C0 1F 00 00 */ lfs f0, 0x0(r31) /* 800B31C8 000AF008 ED 02 30 24 */ fdivs f8, f2, f6 /* 800B31CC 000AF00C EC E0 08 24 */ fdivs f7, f0, f1 .global lbl_800B31D0 lbl_800B31D0: /* 800B31D0 000AF010 FC 00 40 50 */ fneg f0, f8 /* 800B31D4 000AF014 C0 62 8B 54 */ lfs f3, "@6745"@sda21(r2) /* 800B31D8 000AF018 EC 9F 01 F2 */ fmuls f4, f31, f7 /* 800B31DC 000AF01C C0 BF 00 00 */ lfs f5, 0x0(r31) /* 800B31E0 000AF020 C0 5F 00 04 */ lfs f2, 0x4(r31) /* 800B31E4 000AF024 EC 20 07 F2 */ fmuls f1, f0, f31 /* 800B31E8 000AF028 C0 1F 00 08 */ lfs f0, 0x8(r31) /* 800B31EC 000AF02C D1 1E 00 00 */ stfs f8, 0x0(r30) /* 800B31F0 000AF030 D0 BE 00 04 */ stfs f5, 0x4(r30) /* 800B31F4 000AF034 D0 9E 00 08 */ stfs f4, 0x8(r30) /* 800B31F8 000AF038 D0 7E 00 0C */ stfs f3, 0xc(r30) /* 800B31FC 000AF03C D0 FE 00 10 */ stfs f7, 0x10(r30) /* 800B3200 000AF040 D0 5E 00 14 */ stfs f2, 0x14(r30) /* 800B3204 000AF044 D0 3E 00 18 */ stfs f1, 0x18(r30) /* 800B3208 000AF048 D0 7E 00 1C */ stfs f3, 0x1c(r30) /* 800B320C 000AF04C D0 7E 00 20 */ stfs f3, 0x20(r30) /* 800B3210 000AF050 D0 1E 00 24 */ stfs f0, 0x24(r30) /* 800B3214 000AF054 D0 DE 00 28 */ stfs f6, 0x28(r30) /* 800B3218 000AF058 D0 7E 00 2C */ stfs f3, 0x2c(r30) /* 800B321C 000AF05C E3 E1 00 28 */ psq_l f31, 0x28(r1), 0, qr0 /* 800B3220 000AF060 CB E1 00 20 */ lfd f31, 0x20(r1) /* 800B3224 000AF064 E3 C1 00 18 */ psq_l f30, 0x18(r1), 0, qr0 /* 800B3228 000AF068 CB C1 00 10 */ lfd f30, 0x10(r1) /* 800B322C 000AF06C 83 E1 00 0C */ lwz r31, 0xc(r1) /* 800B3230 000AF070 83 C1 00 08 */ lwz r30, 0x8(r1) /* 800B3234 000AF074 80 01 00 34 */ lwz r0, 0x34(r1) /* 800B3238 000AF078 7C 08 03 A6 */ mtlr r0 /* 800B323C 000AF07C 38 21 00 30 */ addi r1, r1, 0x30 /* 800B3240 000AF080 4E 80 00 20 */ blr /* 800B3244 000AF084 00 00 00 00 */ .4byte 0x00000000 /* 800B3248 000AF088 00 00 00 00 */ .4byte 0x00000000 /* 800B324C 000AF08C 00 00 00 00 */ .4byte 0x00000000 .global MtxGetRotationMtx__Q24nw4r2efFRCQ34nw4r4math5MTX34PQ34nw4r4math5MTX34 MtxGetRotationMtx__Q24nw4r2efFRCQ34nw4r4math5MTX34PQ34nw4r4math5MTX34: /* 800B3250 000AF090 94 21 FF C0 */ stwu r1, -0x40(r1) /* 800B3254 000AF094 7C 08 02 A6 */ mflr r0 /* 800B3258 000AF098 C0 43 00 00 */ lfs f2, 0x0(r3) /* 800B325C 000AF09C 90 01 00 44 */ stw r0, 0x44(r1) /* 800B3260 000AF0A0 C0 23 00 10 */ lfs f1, 0x10(r3) /* 800B3264 000AF0A4 93 E1 00 3C */ stw r31, 0x3c(r1) /* 800B3268 000AF0A8 7C 9F 23 78 */ mr r31, r4 /* 800B326C 000AF0AC C0 03 00 20 */ lfs f0, 0x20(r3) /* 800B3270 000AF0B0 93 C1 00 38 */ stw r30, 0x38(r1) /* 800B3274 000AF0B4 7C 7E 1B 78 */ mr r30, r3 /* 800B3278 000AF0B8 38 61 00 20 */ addi r3, r1, 0x20 /* 800B327C 000AF0BC D0 41 00 20 */ stfs f2, 0x20(r1) /* 800B3280 000AF0C0 7C 64 1B 78 */ mr r4, r3 /* 800B3284 000AF0C4 D0 21 00 24 */ stfs f1, 0x24(r1) /* 800B3288 000AF0C8 D0 01 00 28 */ stfs f0, 0x28(r1) /* 800B328C 000AF0CC 48 00 07 45 */ bl Normalize__Q24nw4r2efFPQ34nw4r4math4VEC3PCQ34nw4r4math4VEC3 /* 800B3290 000AF0D0 2C 03 00 00 */ cmpwi r3, 0x0 /* 800B3294 000AF0D4 40 82 00 0C */ bne lbl_800B32A0 /* 800B3298 000AF0D8 C0 02 8B 4C */ lfs f0, "@6743"@sda21(r2) /* 800B329C 000AF0DC D0 01 00 20 */ stfs f0, 0x20(r1) .global lbl_800B32A0 lbl_800B32A0: /* 800B32A0 000AF0E0 C0 5E 00 04 */ lfs f2, 0x4(r30) /* 800B32A4 000AF0E4 38 61 00 14 */ addi r3, r1, 0x14 /* 800B32A8 000AF0E8 C0 3E 00 14 */ lfs f1, 0x14(r30) /* 800B32AC 000AF0EC 7C 64 1B 78 */ mr r4, r3 /* 800B32B0 000AF0F0 C0 1E 00 24 */ lfs f0, 0x24(r30) /* 800B32B4 000AF0F4 D0 41 00 14 */ stfs f2, 0x14(r1) /* 800B32B8 000AF0F8 D0 21 00 18 */ stfs f1, 0x18(r1) /* 800B32BC 000AF0FC D0 01 00 1C */ stfs f0, 0x1c(r1) /* 800B32C0 000AF100 48 00 07 11 */ bl Normalize__Q24nw4r2efFPQ34nw4r4math4VEC3PCQ34nw4r4math4VEC3 /* 800B32C4 000AF104 2C 03 00 00 */ cmpwi r3, 0x0 /* 800B32C8 000AF108 40 82 00 0C */ bne lbl_800B32D4 /* 800B32CC 000AF10C C0 02 8B 4C */ lfs f0, "@6743"@sda21(r2) /* 800B32D0 000AF110 D0 01 00 18 */ stfs f0, 0x18(r1) .global lbl_800B32D4 lbl_800B32D4: /* 800B32D4 000AF114 38 61 00 20 */ addi r3, r1, 0x20 /* 800B32D8 000AF118 38 81 00 14 */ addi r4, r1, 0x14 /* 800B32DC 000AF11C 38 A1 00 08 */ addi r5, r1, 0x8 /* 800B32E0 000AF120 4B F7 E3 81 */ bl PSVECCrossProduct /* 800B32E4 000AF124 38 61 00 08 */ addi r3, r1, 0x8 /* 800B32E8 000AF128 38 81 00 20 */ addi r4, r1, 0x20 /* 800B32EC 000AF12C 38 A1 00 14 */ addi r5, r1, 0x14 /* 800B32F0 000AF130 4B F7 E3 71 */ bl PSVECCrossProduct /* 800B32F4 000AF134 C0 01 00 20 */ lfs f0, 0x20(r1) /* 800B32F8 000AF138 D0 1F 00 00 */ stfs f0, 0x0(r31) /* 800B32FC 000AF13C C0 02 8B 54 */ lfs f0, "@6745"@sda21(r2) /* 800B3300 000AF140 C0 21 00 24 */ lfs f1, 0x24(r1) /* 800B3304 000AF144 D0 3F 00 10 */ stfs f1, 0x10(r31) /* 800B3308 000AF148 C0 21 00 28 */ lfs f1, 0x28(r1) /* 800B330C 000AF14C D0 3F 00 20 */ stfs f1, 0x20(r31) /* 800B3310 000AF150 C0 21 00 14 */ lfs f1, 0x14(r1) /* 800B3314 000AF154 D0 3F 00 04 */ stfs f1, 0x4(r31) /* 800B3318 000AF158 C0 21 00 18 */ lfs f1, 0x18(r1) /* 800B331C 000AF15C D0 3F 00 14 */ stfs f1, 0x14(r31) /* 800B3320 000AF160 C0 21 00 1C */ lfs f1, 0x1c(r1) /* 800B3324 000AF164 D0 3F 00 24 */ stfs f1, 0x24(r31) /* 800B3328 000AF168 C0 21 00 08 */ lfs f1, 0x8(r1) /* 800B332C 000AF16C D0 3F 00 08 */ stfs f1, 0x8(r31) /* 800B3330 000AF170 C0 21 00 0C */ lfs f1, 0xc(r1) /* 800B3334 000AF174 D0 3F 00 18 */ stfs f1, 0x18(r31) /* 800B3338 000AF178 C0 21 00 10 */ lfs f1, 0x10(r1) /* 800B333C 000AF17C D0 3F 00 28 */ stfs f1, 0x28(r31) /* 800B3340 000AF180 D0 1F 00 0C */ stfs f0, 0xc(r31) /* 800B3344 000AF184 D0 1F 00 1C */ stfs f0, 0x1c(r31) /* 800B3348 000AF188 D0 1F 00 2C */ stfs f0, 0x2c(r31) /* 800B334C 000AF18C 83 E1 00 3C */ lwz r31, 0x3c(r1) /* 800B3350 000AF190 83 C1 00 38 */ lwz r30, 0x38(r1) /* 800B3354 000AF194 80 01 00 44 */ lwz r0, 0x44(r1) /* 800B3358 000AF198 7C 08 03 A6 */ mtlr r0 /* 800B335C 000AF19C 38 21 00 40 */ addi r1, r1, 0x40 /* 800B3360 000AF1A0 4E 80 00 20 */ blr /* 800B3364 000AF1A4 00 00 00 00 */ .4byte 0x00000000 /* 800B3368 000AF1A8 00 00 00 00 */ .4byte 0x00000000 /* 800B336C 000AF1AC 00 00 00 00 */ .4byte 0x00000000 .global MtxGetRotation__Q24nw4r2efFRCQ34nw4r4math5MTX34PQ34nw4r4math4VEC3 MtxGetRotation__Q24nw4r2efFRCQ34nw4r4math5MTX34PQ34nw4r4math4VEC3: /* 800B3370 000AF1B0 94 21 FF C0 */ stwu r1, -0x40(r1) /* 800B3374 000AF1B4 7C 08 02 A6 */ mflr r0 /* 800B3378 000AF1B8 90 01 00 44 */ stw r0, 0x44(r1) /* 800B337C 000AF1BC DB E1 00 30 */ stfd f31, 0x30(r1) /* 800B3380 000AF1C0 F3 E1 00 38 */ psq_st f31, 0x38(r1), 0, qr0 /* 800B3384 000AF1C4 DB C1 00 20 */ stfd f30, 0x20(r1) /* 800B3388 000AF1C8 F3 C1 00 28 */ psq_st f30, 0x28(r1), 0, qr0 /* 800B338C 000AF1CC DB A1 00 10 */ stfd f29, 0x10(r1) /* 800B3390 000AF1D0 F3 A1 00 18 */ psq_st f29, 0x18(r1), 0, qr0 /* 800B3394 000AF1D4 93 E1 00 0C */ stw r31, 0xc(r1) /* 800B3398 000AF1D8 7C 9F 23 78 */ mr r31, r4 /* 800B339C 000AF1DC 38 80 00 00 */ li r4, 0x0 /* 800B33A0 000AF1E0 93 C1 00 08 */ stw r30, 0x8(r1) /* 800B33A4 000AF1E4 7C 7E 1B 78 */ mr r30, r3 /* 800B33A8 000AF1E8 48 00 0C 29 */ bl MTXColLen__Q24nw4r2efFPCQ34nw4r4math5MTX34i /* 800B33AC 000AF1EC C0 02 8B 58 */ lfs f0, "@6793_8055EAD8"@sda21(r2) /* 800B33B0 000AF1F0 FF A0 08 90 */ fmr f29, f1 /* 800B33B4 000AF1F4 FC 01 00 40 */ fcmpo cr0, f1, f0 /* 800B33B8 000AF1F8 41 80 00 E4 */ blt lbl_800B349C /* 800B33BC 000AF1FC 7F C3 F3 78 */ mr r3, r30 /* 800B33C0 000AF200 38 80 00 01 */ li r4, 0x1 /* 800B33C4 000AF204 48 00 0C 0D */ bl MTXColLen__Q24nw4r2efFPCQ34nw4r4math5MTX34i /* 800B33C8 000AF208 C0 02 8B 58 */ lfs f0, "@6793_8055EAD8"@sda21(r2) /* 800B33CC 000AF20C FF C0 08 90 */ fmr f30, f1 /* 800B33D0 000AF210 FC 01 00 40 */ fcmpo cr0, f1, f0 /* 800B33D4 000AF214 41 80 00 C8 */ blt lbl_800B349C /* 800B33D8 000AF218 7F C3 F3 78 */ mr r3, r30 /* 800B33DC 000AF21C 38 80 00 02 */ li r4, 0x2 /* 800B33E0 000AF220 48 00 0B F1 */ bl MTXColLen__Q24nw4r2efFPCQ34nw4r4math5MTX34i /* 800B33E4 000AF224 C0 02 8B 58 */ lfs f0, "@6793_8055EAD8"@sda21(r2) /* 800B33E8 000AF228 FF E0 08 90 */ fmr f31, f1 /* 800B33EC 000AF22C FC 01 00 40 */ fcmpo cr0, f1, f0 /* 800B33F0 000AF230 41 80 00 AC */ blt lbl_800B349C /* 800B33F4 000AF234 C0 3E 00 20 */ lfs f1, 0x20(r30) /* 800B33F8 000AF238 C0 02 8B 4C */ lfs f0, "@6743"@sda21(r2) /* 800B33FC 000AF23C FC 20 08 50 */ fneg f1, f1 /* 800B3400 000AF240 EC 21 E8 24 */ fdivs f1, f1, f29 /* 800B3404 000AF244 FC 01 00 40 */ fcmpo cr0, f1, f0 /* 800B3408 000AF248 40 81 00 08 */ ble lbl_800B3410 /* 800B340C 000AF24C FC 20 00 90 */ fmr f1, f0 .global lbl_800B3410 lbl_800B3410: /* 800B3410 000AF250 C0 02 8B 5C */ lfs f0, "@6794_8055EADC"@sda21(r2) /* 800B3414 000AF254 FC 01 00 40 */ fcmpo cr0, f1, f0 /* 800B3418 000AF258 40 80 00 08 */ bge lbl_800B3420 /* 800B341C 000AF25C FC 20 00 90 */ fmr f1, f0 .global lbl_800B3420 lbl_800B3420: /* 800B3420 000AF260 4B F6 11 6D */ bl asin /* 800B3424 000AF264 FC 20 08 18 */ frsp f1, f1 /* 800B3428 000AF268 C0 02 8B 48 */ lfs f0, "@6728"@sda21(r2) /* 800B342C 000AF26C D0 3F 00 04 */ stfs f1, 0x4(r31) /* 800B3430 000AF270 EC 20 00 72 */ fmuls f1, f0, f1 /* 800B3434 000AF274 48 04 B6 ED */ bl CosFIdx__Q24nw4r4mathFf /* 800B3438 000AF278 C0 02 8B 58 */ lfs f0, "@6793_8055EAD8"@sda21(r2) /* 800B343C 000AF27C FC 01 00 40 */ fcmpo cr0, f1, f0 /* 800B3440 000AF280 4C 41 13 82 */ cror eq, gt, eq /* 800B3444 000AF284 40 82 00 38 */ bne lbl_800B347C /* 800B3448 000AF288 C0 3E 00 28 */ lfs f1, 0x28(r30) /* 800B344C 000AF28C C0 1E 00 24 */ lfs f0, 0x24(r30) /* 800B3450 000AF290 EC 41 F8 24 */ fdivs f2, f1, f31 /* 800B3454 000AF294 EC 20 F0 24 */ fdivs f1, f0, f30 /* 800B3458 000AF298 4B F6 11 39 */ bl atan2 /* 800B345C 000AF29C FC 00 08 18 */ frsp f0, f1 /* 800B3460 000AF2A0 D0 1F 00 00 */ stfs f0, 0x0(r31) /* 800B3464 000AF2A4 C0 5E 00 00 */ lfs f2, 0x0(r30) /* 800B3468 000AF2A8 C0 3E 00 10 */ lfs f1, 0x10(r30) /* 800B346C 000AF2AC 4B F6 11 25 */ bl atan2 /* 800B3470 000AF2B0 FC 00 08 18 */ frsp f0, f1 /* 800B3474 000AF2B4 D0 1F 00 08 */ stfs f0, 0x8(r31) /* 800B3478 000AF2B8 48 00 00 34 */ b lbl_800B34AC .global lbl_800B347C lbl_800B347C: /* 800B347C 000AF2BC C0 5E 00 14 */ lfs f2, 0x14(r30) /* 800B3480 000AF2C0 C0 3E 00 04 */ lfs f1, 0x4(r30) /* 800B3484 000AF2C4 4B F6 11 0D */ bl atan2 /* 800B3488 000AF2C8 FC 20 08 18 */ frsp f1, f1 /* 800B348C 000AF2CC C0 02 8B 54 */ lfs f0, "@6745"@sda21(r2) /* 800B3490 000AF2D0 D0 1F 00 08 */ stfs f0, 0x8(r31) /* 800B3494 000AF2D4 D0 3F 00 00 */ stfs f1, 0x0(r31) /* 800B3498 000AF2D8 48 00 00 14 */ b lbl_800B34AC .global lbl_800B349C lbl_800B349C: /* 800B349C 000AF2DC C0 02 8B 54 */ lfs f0, "@6745"@sda21(r2) /* 800B34A0 000AF2E0 D0 1F 00 00 */ stfs f0, 0x0(r31) /* 800B34A4 000AF2E4 D0 1F 00 04 */ stfs f0, 0x4(r31) /* 800B34A8 000AF2E8 D0 1F 00 08 */ stfs f0, 0x8(r31) .global lbl_800B34AC lbl_800B34AC: /* 800B34AC 000AF2EC 80 01 00 44 */ lwz r0, 0x44(r1) /* 800B34B0 000AF2F0 E3 E1 00 38 */ psq_l f31, 0x38(r1), 0, qr0 /* 800B34B4 000AF2F4 CB E1 00 30 */ lfd f31, 0x30(r1) /* 800B34B8 000AF2F8 E3 C1 00 28 */ psq_l f30, 0x28(r1), 0, qr0 /* 800B34BC 000AF2FC CB C1 00 20 */ lfd f30, 0x20(r1) /* 800B34C0 000AF300 E3 A1 00 18 */ psq_l f29, 0x18(r1), 0, qr0 /* 800B34C4 000AF304 CB A1 00 10 */ lfd f29, 0x10(r1) /* 800B34C8 000AF308 83 E1 00 0C */ lwz r31, 0xc(r1) /* 800B34CC 000AF30C 83 C1 00 08 */ lwz r30, 0x8(r1) /* 800B34D0 000AF310 7C 08 03 A6 */ mtlr r0 /* 800B34D4 000AF314 38 21 00 40 */ addi r1, r1, 0x40 /* 800B34D8 000AF318 4E 80 00 20 */ blr /* 800B34DC 000AF31C 00 00 00 00 */ .4byte 0x00000000 .global MtxGetTranslate__Q24nw4r2efFRCQ34nw4r4math5MTX34PQ34nw4r4math4VEC3 MtxGetTranslate__Q24nw4r2efFRCQ34nw4r4math5MTX34PQ34nw4r4math4VEC3: /* 800B34E0 000AF320 C0 43 00 0C */ lfs f2, 0xc(r3) /* 800B34E4 000AF324 C0 23 00 1C */ lfs f1, 0x1c(r3) /* 800B34E8 000AF328 C0 03 00 2C */ lfs f0, 0x2c(r3) /* 800B34EC 000AF32C D0 44 00 00 */ stfs f2, 0x0(r4) /* 800B34F0 000AF330 D0 24 00 04 */ stfs f1, 0x4(r4) /* 800B34F4 000AF334 D0 04 00 08 */ stfs f0, 0x8(r4) /* 800B34F8 000AF338 4E 80 00 20 */ blr /* 800B34FC 000AF33C 00 00 00 00 */ .4byte 0x00000000 .global MtxGetScale__Q24nw4r2efFRCQ34nw4r4math5MTX34PQ34nw4r4math4VEC3 MtxGetScale__Q24nw4r2efFRCQ34nw4r4math5MTX34PQ34nw4r4math4VEC3: /* 800B3500 000AF340 94 21 FF 90 */ stwu r1, -0x70(r1) /* 800B3504 000AF344 7C 08 02 A6 */ mflr r0 /* 800B3508 000AF348 90 01 00 74 */ stw r0, 0x74(r1) /* 800B350C 000AF34C 39 61 00 60 */ addi r11, r1, 0x60 /* 800B3510 000AF350 DB E1 00 60 */ stfd f31, 0x60(r1) /* 800B3514 000AF354 F3 E1 00 68 */ psq_st f31, 0x68(r1), 0, qr0 /* 800B3518 000AF358 4B F5 3E 25 */ bl lbl_8000733C /* 800B351C 000AF35C C0 03 00 00 */ lfs f0, 0x0(r3) /* 800B3520 000AF360 3B E1 00 2C */ addi r31, r1, 0x2c /* 800B3524 000AF364 C0 23 00 10 */ lfs f1, 0x10(r3) /* 800B3528 000AF368 7C 7B 1B 78 */ mr r27, r3 /* 800B352C 000AF36C D0 01 00 2C */ stfs f0, 0x2c(r1) /* 800B3530 000AF370 7C 9C 23 78 */ mr r28, r4 /* 800B3534 000AF374 C0 03 00 20 */ lfs f0, 0x20(r3) /* 800B3538 000AF378 D0 21 00 30 */ stfs f1, 0x30(r1) /* 800B353C 000AF37C C0 62 8B 50 */ lfs f3, "@6744"@sda21(r2) /* 800B3540 000AF380 E0 5F 00 00 */ psq_l f2, 0x0(r31), 0, qr0 /* 800B3544 000AF384 D0 01 00 34 */ stfs f0, 0x34(r1) /* 800B3548 000AF388 10 42 00 B2 */ ps_mul f2, f2, f2 /* 800B354C 000AF38C 10 20 10 3A */ ps_madd f1, f0, f0, f2 /* 800B3550 000AF390 10 21 10 94 */ ps_sum0 f1, f1, f2, f2 /* 800B3554 000AF394 FC 01 18 40 */ fcmpo cr0, f1, f3 /* 800B3558 000AF398 40 81 03 44 */ ble lbl_800B389C /* 800B355C 000AF39C 48 04 B5 15 */ bl FrSqrt__Q24nw4r4mathFf /* 800B3560 000AF3A0 EC C0 08 30 */ fres f6, f1 /* 800B3564 000AF3A4 E1 1F 00 00 */ psq_l f8, 0x0(r31), 0, qr0 /* 800B3568 000AF3A8 C0 5B 00 14 */ lfs f2, 0x14(r27) /* 800B356C 000AF3AC 3B C1 00 20 */ addi r30, r1, 0x20 /* 800B3570 000AF3B0 C0 1B 00 24 */ lfs f0, 0x24(r27) /* 800B3574 000AF3B4 3B A1 00 08 */ addi r29, r1, 0x8 /* 800B3578 000AF3B8 10 E8 00 58 */ ps_muls0 f7, f8, f1 /* 800B357C 000AF3BC E1 1F 80 08 */ psq_l f8, 0x8(r31), 1, qr0 /* 800B3580 000AF3C0 10 A6 30 2A */ ps_add f5, f6, f6 /* 800B3584 000AF3C4 C0 9B 00 04 */ lfs f4, 0x4(r27) /* 800B3588 000AF3C8 F0 FF 00 00 */ psq_st f7, 0x0(r31), 0, qr0 /* 800B358C 000AF3CC 10 E8 00 58 */ ps_muls0 f7, f8, f1 /* 800B3590 000AF3D0 10 66 01 B2 */ ps_mul f3, f6, f6 /* 800B3594 000AF3D4 F0 FF 80 08 */ psq_st f7, 0x8(r31), 1, qr0 /* 800B3598 000AF3D8 E1 1F 80 00 */ psq_l f8, 0x0(r31), 1, qr0 /* 800B359C 000AF3DC E1 3F 00 00 */ psq_l f9, 0x0(r31), 0, qr0 /* 800B35A0 000AF3E0 10 C1 28 FC */ ps_nmsub f6, f1, f3, f5 /* 800B35A4 000AF3E4 E0 BF 00 04 */ psq_l f5, 0x4(r31), 0, qr0 /* 800B35A8 000AF3E8 C0 62 8B 50 */ lfs f3, "@6744"@sda21(r2) /* 800B35AC 000AF3EC D0 DC 00 00 */ stfs f6, 0x0(r28) /* 800B35B0 000AF3F0 D0 81 00 20 */ stfs f4, 0x20(r1) /* 800B35B4 000AF3F4 D0 41 00 24 */ stfs f2, 0x24(r1) /* 800B35B8 000AF3F8 E0 3E 80 00 */ psq_l f1, 0x0(r30), 1, qr0 /* 800B35BC 000AF3FC D0 01 00 28 */ stfs f0, 0x28(r1) /* 800B35C0 000AF400 E0 5E 00 00 */ psq_l f2, 0x0(r30), 0, qr0 /* 800B35C4 000AF404 E0 1E 00 04 */ psq_l f0, 0x4(r30), 0, qr0 /* 800B35C8 000AF408 10 A5 00 32 */ ps_mul f5, f5, f0 /* 800B35CC 000AF40C 10 08 28 7A */ ps_madd f0, f8, f1, f5 /* 800B35D0 000AF410 10 00 29 54 */ ps_sum0 f0, f0, f5, f5 /* 800B35D4 000AF414 D0 01 00 38 */ stfs f0, 0x38(r1) /* 800B35D8 000AF418 FC 00 00 18 */ frsp f0, f0 /* 800B35DC 000AF41C 10 29 00 18 */ ps_muls0 f1, f9, f0 /* 800B35E0 000AF420 F0 3D 00 00 */ psq_st f1, 0x0(r29), 0, qr0 /* 800B35E4 000AF424 10 27 00 18 */ ps_muls0 f1, f7, f0 /* 800B35E8 000AF428 E0 1D 00 00 */ psq_l f0, 0x0(r29), 0, qr0 /* 800B35EC 000AF42C F0 3D 80 08 */ psq_st f1, 0x8(r29), 1, qr0 /* 800B35F0 000AF430 10 02 00 28 */ ps_sub f0, f2, f0 /* 800B35F4 000AF434 E0 5E 80 08 */ psq_l f2, 0x8(r30), 1, qr0 /* 800B35F8 000AF438 F0 1E 00 00 */ psq_st f0, 0x0(r30), 0, qr0 /* 800B35FC 000AF43C 10 02 08 28 */ ps_sub f0, f2, f1 /* 800B3600 000AF440 E0 5E 00 00 */ psq_l f2, 0x0(r30), 0, qr0 /* 800B3604 000AF444 F0 1E 80 08 */ psq_st f0, 0x8(r30), 1, qr0 /* 800B3608 000AF448 10 42 00 B2 */ ps_mul f2, f2, f2 /* 800B360C 000AF44C C0 01 00 28 */ lfs f0, 0x28(r1) /* 800B3610 000AF450 10 20 10 3A */ ps_madd f1, f0, f0, f2 /* 800B3614 000AF454 10 21 10 94 */ ps_sum0 f1, f1, f2, f2 /* 800B3618 000AF458 FC 01 18 40 */ fcmpo cr0, f1, f3 /* 800B361C 000AF45C 40 81 01 C8 */ ble lbl_800B37E4 /* 800B3620 000AF460 48 04 B4 51 */ bl FrSqrt__Q24nw4r4mathFf /* 800B3624 000AF464 EC C0 08 30 */ fres f6, f1 /* 800B3628 000AF468 C0 01 00 38 */ lfs f0, 0x38(r1) /* 800B362C 000AF46C C0 7B 00 18 */ lfs f3, 0x18(r27) /* 800B3630 000AF470 38 61 00 14 */ addi r3, r1, 0x14 /* 800B3634 000AF474 C0 5B 00 28 */ lfs f2, 0x28(r27) /* 800B3638 000AF478 C0 9B 00 08 */ lfs f4, 0x8(r27) /* 800B363C 000AF47C 10 E6 30 2A */ ps_add f7, f6, f6 /* 800B3640 000AF480 E1 3F 00 04 */ psq_l f9, 0x4(r31), 0, qr0 /* 800B3644 000AF484 10 C6 01 B2 */ ps_mul f6, f6, f6 /* 800B3648 000AF488 E1 1F 80 00 */ psq_l f8, 0x0(r31), 1, qr0 /* 800B364C 000AF48C EC A0 00 72 */ fmuls f5, f0, f1 /* 800B3650 000AF490 E1 5F 00 00 */ psq_l f10, 0x0(r31), 0, qr0 /* 800B3654 000AF494 10 C1 39 BC */ ps_nmsub f6, f1, f6, f7 /* 800B3658 000AF498 D0 A1 00 38 */ stfs f5, 0x38(r1) /* 800B365C 000AF49C C0 02 8B 50 */ lfs f0, "@6744"@sda21(r2) /* 800B3660 000AF4A0 D0 DC 00 04 */ stfs f6, 0x4(r28) /* 800B3664 000AF4A4 E0 BE 00 00 */ psq_l f5, 0x0(r30), 0, qr0 /* 800B3668 000AF4A8 D0 61 00 18 */ stfs f3, 0x18(r1) /* 800B366C 000AF4AC 10 65 00 58 */ ps_muls0 f3, f5, f1 /* 800B3670 000AF4B0 E0 BE 80 08 */ psq_l f5, 0x8(r30), 1, qr0 /* 800B3674 000AF4B4 D0 41 00 1C */ stfs f2, 0x1c(r1) /* 800B3678 000AF4B8 F0 7E 00 00 */ psq_st f3, 0x0(r30), 0, qr0 /* 800B367C 000AF4BC 10 65 00 58 */ ps_muls0 f3, f5, f1 /* 800B3680 000AF4C0 E0 A3 00 04 */ psq_l f5, 0x4(r3), 0, qr0 /* 800B3684 000AF4C4 D0 81 00 14 */ stfs f4, 0x14(r1) /* 800B3688 000AF4C8 E0 3E 80 00 */ psq_l f1, 0x0(r30), 1, qr0 /* 800B368C 000AF4CC F0 7E 80 08 */ psq_st f3, 0x8(r30), 1, qr0 /* 800B3690 000AF4D0 E0 43 80 00 */ psq_l f2, 0x0(r3), 1, qr0 /* 800B3694 000AF4D4 E0 9E 00 04 */ psq_l f4, 0x4(r30), 0, qr0 /* 800B3698 000AF4D8 E0 DE 00 00 */ psq_l f6, 0x0(r30), 0, qr0 /* 800B369C 000AF4DC 10 84 01 72 */ ps_mul f4, f4, f5 /* 800B36A0 000AF4E0 E0 E3 00 00 */ psq_l f7, 0x0(r3), 0, qr0 /* 800B36A4 000AF4E4 10 A1 20 BA */ ps_madd f5, f1, f2, f4 /* 800B36A8 000AF4E8 10 25 21 14 */ ps_sum0 f1, f5, f4, f4 /* 800B36AC 000AF4EC D0 21 00 40 */ stfs f1, 0x40(r1) /* 800B36B0 000AF4F0 FC 20 08 18 */ frsp f1, f1 /* 800B36B4 000AF4F4 10 46 00 58 */ ps_muls0 f2, f6, f1 /* 800B36B8 000AF4F8 F0 5D 00 00 */ psq_st f2, 0x0(r29), 0, qr0 /* 800B36BC 000AF4FC 10 43 00 58 */ ps_muls0 f2, f3, f1 /* 800B36C0 000AF500 E0 3D 00 00 */ psq_l f1, 0x0(r29), 0, qr0 /* 800B36C4 000AF504 10 27 08 28 */ ps_sub f1, f7, f1 /* 800B36C8 000AF508 E0 E3 80 08 */ psq_l f7, 0x8(r3), 1, qr0 /* 800B36CC 000AF50C F0 23 00 00 */ psq_st f1, 0x0(r3), 0, qr0 /* 800B36D0 000AF510 10 27 10 28 */ ps_sub f1, f7, f2 /* 800B36D4 000AF514 F0 23 80 08 */ psq_st f1, 0x8(r3), 1, qr0 /* 800B36D8 000AF518 E0 43 80 00 */ psq_l f2, 0x0(r3), 1, qr0 /* 800B36DC 000AF51C E0 63 00 04 */ psq_l f3, 0x4(r3), 0, qr0 /* 800B36E0 000AF520 E0 83 00 00 */ psq_l f4, 0x0(r3), 0, qr0 /* 800B36E4 000AF524 11 29 00 F2 */ ps_mul f9, f9, f3 /* 800B36E8 000AF528 10 68 48 BA */ ps_madd f3, f8, f2, f9 /* 800B36EC 000AF52C 10 43 4A 54 */ ps_sum0 f2, f3, f9, f9 /* 800B36F0 000AF530 D0 41 00 3C */ stfs f2, 0x3c(r1) /* 800B36F4 000AF534 FC 40 10 18 */ frsp f2, f2 /* 800B36F8 000AF538 10 6A 00 98 */ ps_muls0 f3, f10, f2 /* 800B36FC 000AF53C E1 5F 80 08 */ psq_l f10, 0x8(r31), 1, qr0 /* 800B3700 000AF540 F0 7D 00 00 */ psq_st f3, 0x0(r29), 0, qr0 /* 800B3704 000AF544 10 6A 00 98 */ ps_muls0 f3, f10, f2 /* 800B3708 000AF548 E0 5D 00 00 */ psq_l f2, 0x0(r29), 0, qr0 /* 800B370C 000AF54C F0 7D 80 08 */ psq_st f3, 0x8(r29), 1, qr0 /* 800B3710 000AF550 10 44 10 28 */ ps_sub f2, f4, f2 /* 800B3714 000AF554 F0 43 00 00 */ psq_st f2, 0x0(r3), 0, qr0 /* 800B3718 000AF558 10 41 18 28 */ ps_sub f2, f1, f3 /* 800B371C 000AF55C E0 63 00 00 */ psq_l f3, 0x0(r3), 0, qr0 /* 800B3720 000AF560 F0 43 80 08 */ psq_st f2, 0x8(r3), 1, qr0 /* 800B3724 000AF564 10 63 00 F2 */ ps_mul f3, f3, f3 /* 800B3728 000AF568 C0 21 00 1C */ lfs f1, 0x1c(r1) /* 800B372C 000AF56C 13 E1 18 7A */ ps_madd f31, f1, f1, f3 /* 800B3730 000AF570 13 FF 18 D4 */ ps_sum0 f31, f31, f3, f3 /* 800B3734 000AF574 FC 1F 00 40 */ fcmpo cr0, f31, f0 /* 800B3738 000AF578 40 81 00 A0 */ ble lbl_800B37D8 /* 800B373C 000AF57C C0 02 8B 54 */ lfs f0, "@6745"@sda21(r2) /* 800B3740 000AF580 FC 1F 00 40 */ fcmpo cr0, f31, f0 /* 800B3744 000AF584 4C 40 13 82 */ cror eq, lt, eq /* 800B3748 000AF588 40 82 00 08 */ bne lbl_800B3750 /* 800B374C 000AF58C 48 00 00 10 */ b lbl_800B375C .global lbl_800B3750 lbl_800B3750: /* 800B3750 000AF590 FC 20 F8 90 */ fmr f1, f31 /* 800B3754 000AF594 48 04 B3 1D */ bl FrSqrt__Q24nw4r4mathFf /* 800B3758 000AF598 EC 1F 00 72 */ fmuls f0, f31, f1 .global lbl_800B375C lbl_800B375C: /* 800B375C 000AF59C D0 1C 00 08 */ stfs f0, 0x8(r28) /* 800B3760 000AF5A0 38 61 00 20 */ addi r3, r1, 0x20 /* 800B3764 000AF5A4 38 81 00 14 */ addi r4, r1, 0x14 /* 800B3768 000AF5A8 38 A1 00 08 */ addi r5, r1, 0x8 /* 800B376C 000AF5AC 4B F7 DE F5 */ bl PSVECCrossProduct /* 800B3770 000AF5B0 38 61 00 2C */ addi r3, r1, 0x2c /* 800B3774 000AF5B4 38 81 00 08 */ addi r4, r1, 0x8 /* 800B3778 000AF5B8 E0 63 00 04 */ psq_l f3, 0x4(r3), 0, qr0 /* 800B377C 000AF5BC E0 44 00 04 */ psq_l f2, 0x4(r4), 0, qr0 /* 800B3780 000AF5C0 E0 23 80 00 */ psq_l f1, 0x0(r3), 1, qr0 /* 800B3784 000AF5C4 10 63 00 B2 */ ps_mul f3, f3, f2 /* 800B3788 000AF5C8 E0 44 80 00 */ psq_l f2, 0x0(r4), 1, qr0 /* 800B378C 000AF5CC C0 02 8B 54 */ lfs f0, "@6745"@sda21(r2) /* 800B3790 000AF5D0 10 41 18 BA */ ps_madd f2, f1, f2, f3 /* 800B3794 000AF5D4 10 22 18 D4 */ ps_sum0 f1, f2, f3, f3 /* 800B3798 000AF5D8 FC 01 00 40 */ fcmpo cr0, f1, f0 /* 800B379C 000AF5DC 40 80 02 14 */ bge lbl_800B39B0 /* 800B37A0 000AF5E0 C0 5C 00 00 */ lfs f2, 0x0(r28) /* 800B37A4 000AF5E4 C8 62 8B 60 */ lfd f3, "@6866"@sda21(r2) /* 800B37A8 000AF5E8 C0 3C 00 04 */ lfs f1, 0x4(r28) /* 800B37AC 000AF5EC C0 1C 00 08 */ lfs f0, 0x8(r28) /* 800B37B0 000AF5F0 FC 42 00 F2 */ fmul f2, f2, f3 /* 800B37B4 000AF5F4 FC 21 00 F2 */ fmul f1, f1, f3 /* 800B37B8 000AF5F8 FC 00 00 F2 */ fmul f0, f0, f3 /* 800B37BC 000AF5FC FC 40 10 18 */ frsp f2, f2 /* 800B37C0 000AF600 FC 20 08 18 */ frsp f1, f1 /* 800B37C4 000AF604 FC 00 00 18 */ frsp f0, f0 /* 800B37C8 000AF608 D0 5C 00 00 */ stfs f2, 0x0(r28) /* 800B37CC 000AF60C D0 3C 00 04 */ stfs f1, 0x4(r28) /* 800B37D0 000AF610 D0 1C 00 08 */ stfs f0, 0x8(r28) /* 800B37D4 000AF614 48 00 01 DC */ b lbl_800B39B0 .global lbl_800B37D8 lbl_800B37D8: /* 800B37D8 000AF618 C0 02 8B 54 */ lfs f0, "@6745"@sda21(r2) /* 800B37DC 000AF61C D0 1C 00 08 */ stfs f0, 0x8(r28) /* 800B37E0 000AF620 48 00 01 D0 */ b lbl_800B39B0 .global lbl_800B37E4 lbl_800B37E4: /* 800B37E4 000AF624 C0 42 8B 54 */ lfs f2, "@6745"@sda21(r2) /* 800B37E8 000AF628 38 61 00 14 */ addi r3, r1, 0x14 /* 800B37EC 000AF62C D0 5C 00 04 */ stfs f2, 0x4(r28) /* 800B37F0 000AF630 C0 3B 00 18 */ lfs f1, 0x18(r27) /* 800B37F4 000AF634 C0 1B 00 28 */ lfs f0, 0x28(r27) /* 800B37F8 000AF638 D0 21 00 18 */ stfs f1, 0x18(r1) /* 800B37FC 000AF63C C0 3B 00 08 */ lfs f1, 0x8(r27) /* 800B3800 000AF640 D0 21 00 14 */ stfs f1, 0x14(r1) /* 800B3804 000AF644 E0 9F 00 04 */ psq_l f4, 0x4(r31), 0, qr0 /* 800B3808 000AF648 D0 01 00 1C */ stfs f0, 0x1c(r1) /* 800B380C 000AF64C E0 03 80 00 */ psq_l f0, 0x0(r3), 1, qr0 /* 800B3810 000AF650 E0 23 00 04 */ psq_l f1, 0x4(r3), 0, qr0 /* 800B3814 000AF654 E0 A3 00 00 */ psq_l f5, 0x0(r3), 0, qr0 /* 800B3818 000AF658 10 84 00 72 */ ps_mul f4, f4, f1 /* 800B381C 000AF65C 10 28 20 3A */ ps_madd f1, f8, f0, f4 /* 800B3820 000AF660 10 01 21 14 */ ps_sum0 f0, f1, f4, f4 /* 800B3824 000AF664 D0 01 00 3C */ stfs f0, 0x3c(r1) /* 800B3828 000AF668 FC 00 00 18 */ frsp f0, f0 /* 800B382C 000AF66C 10 29 00 18 */ ps_muls0 f1, f9, f0 /* 800B3830 000AF670 F0 3D 00 00 */ psq_st f1, 0x0(r29), 0, qr0 /* 800B3834 000AF674 10 27 00 18 */ ps_muls0 f1, f7, f0 /* 800B3838 000AF678 E0 1D 00 00 */ psq_l f0, 0x0(r29), 0, qr0 /* 800B383C 000AF67C F0 3D 80 08 */ psq_st f1, 0x8(r29), 1, qr0 /* 800B3840 000AF680 10 05 00 28 */ ps_sub f0, f5, f0 /* 800B3844 000AF684 E0 A3 80 08 */ psq_l f5, 0x8(r3), 1, qr0 /* 800B3848 000AF688 F0 03 00 00 */ psq_st f0, 0x0(r3), 0, qr0 /* 800B384C 000AF68C 10 05 08 28 */ ps_sub f0, f5, f1 /* 800B3850 000AF690 E0 23 00 00 */ psq_l f1, 0x0(r3), 0, qr0 /* 800B3854 000AF694 F0 03 80 08 */ psq_st f0, 0x8(r3), 1, qr0 /* 800B3858 000AF698 10 21 00 72 */ ps_mul f1, f1, f1 /* 800B385C 000AF69C C0 01 00 1C */ lfs f0, 0x1c(r1) /* 800B3860 000AF6A0 13 E0 08 3A */ ps_madd f31, f0, f0, f1 /* 800B3864 000AF6A4 13 FF 08 54 */ ps_sum0 f31, f31, f1, f1 /* 800B3868 000AF6A8 FC 1F 18 40 */ fcmpo cr0, f31, f3 /* 800B386C 000AF6AC 40 81 00 28 */ ble lbl_800B3894 /* 800B3870 000AF6B0 FC 1F 10 40 */ fcmpo cr0, f31, f2 /* 800B3874 000AF6B4 4C 40 13 82 */ cror eq, lt, eq /* 800B3878 000AF6B8 40 82 00 08 */ bne lbl_800B3880 /* 800B387C 000AF6BC 48 00 00 10 */ b lbl_800B388C .global lbl_800B3880 lbl_800B3880: /* 800B3880 000AF6C0 FC 20 F8 90 */ fmr f1, f31 /* 800B3884 000AF6C4 48 04 B1 ED */ bl FrSqrt__Q24nw4r4mathFf /* 800B3888 000AF6C8 EC 5F 00 72 */ fmuls f2, f31, f1 .global lbl_800B388C lbl_800B388C: /* 800B388C 000AF6CC D0 5C 00 08 */ stfs f2, 0x8(r28) /* 800B3890 000AF6D0 48 00 01 20 */ b lbl_800B39B0 .global lbl_800B3894 lbl_800B3894: /* 800B3894 000AF6D4 D0 5C 00 08 */ stfs f2, 0x8(r28) /* 800B3898 000AF6D8 48 00 01 18 */ b lbl_800B39B0 .global lbl_800B389C lbl_800B389C: /* 800B389C 000AF6DC C0 42 8B 54 */ lfs f2, "@6745"@sda21(r2) /* 800B38A0 000AF6E0 3B A1 00 20 */ addi r29, r1, 0x20 /* 800B38A4 000AF6E4 D0 44 00 00 */ stfs f2, 0x0(r4) /* 800B38A8 000AF6E8 C0 03 00 04 */ lfs f0, 0x4(r3) /* 800B38AC 000AF6EC C0 23 00 14 */ lfs f1, 0x14(r3) /* 800B38B0 000AF6F0 D0 01 00 20 */ stfs f0, 0x20(r1) /* 800B38B4 000AF6F4 C0 03 00 24 */ lfs f0, 0x24(r3) /* 800B38B8 000AF6F8 D0 21 00 24 */ stfs f1, 0x24(r1) /* 800B38BC 000AF6FC E0 9D 00 00 */ psq_l f4, 0x0(r29), 0, qr0 /* 800B38C0 000AF700 D0 01 00 28 */ stfs f0, 0x28(r1) /* 800B38C4 000AF704 10 84 01 32 */ ps_mul f4, f4, f4 /* 800B38C8 000AF708 10 20 20 3A */ ps_madd f1, f0, f0, f4 /* 800B38CC 000AF70C 10 21 21 14 */ ps_sum0 f1, f1, f4, f4 /* 800B38D0 000AF710 FC 01 18 40 */ fcmpo cr0, f1, f3 /* 800B38D4 000AF714 40 81 00 B4 */ ble lbl_800B3988 /* 800B38D8 000AF718 48 04 B1 99 */ bl FrSqrt__Q24nw4r4mathFf /* 800B38DC 000AF71C EC 80 08 30 */ fres f4, f1 /* 800B38E0 000AF720 C0 7B 00 08 */ lfs f3, 0x8(r27) /* 800B38E4 000AF724 C0 5B 00 18 */ lfs f2, 0x18(r27) /* 800B38E8 000AF728 38 61 00 14 */ addi r3, r1, 0x14 /* 800B38EC 000AF72C C0 1B 00 28 */ lfs f0, 0x28(r27) /* 800B38F0 000AF730 38 81 00 08 */ addi r4, r1, 0x8 /* 800B38F4 000AF734 10 A4 20 2A */ ps_add f5, f4, f4 /* 800B38F8 000AF738 10 84 01 32 */ ps_mul f4, f4, f4 /* 800B38FC 000AF73C 10 81 29 3C */ ps_nmsub f4, f1, f4, f5 /* 800B3900 000AF740 D0 9C 00 04 */ stfs f4, 0x4(r28) /* 800B3904 000AF744 E0 9D 00 00 */ psq_l f4, 0x0(r29), 0, qr0 /* 800B3908 000AF748 D0 61 00 14 */ stfs f3, 0x14(r1) /* 800B390C 000AF74C 10 64 00 58 */ ps_muls0 f3, f4, f1 /* 800B3910 000AF750 E0 9D 80 08 */ psq_l f4, 0x8(r29), 1, qr0 /* 800B3914 000AF754 D0 41 00 18 */ stfs f2, 0x18(r1) /* 800B3918 000AF758 E0 43 80 00 */ psq_l f2, 0x0(r3), 1, qr0 /* 800B391C 000AF75C F0 7D 00 00 */ psq_st f3, 0x0(r29), 0, qr0 /* 800B3920 000AF760 10 64 00 58 */ ps_muls0 f3, f4, f1 /* 800B3924 000AF764 E0 C3 00 00 */ psq_l f6, 0x0(r3), 0, qr0 /* 800B3928 000AF768 F0 7D 80 08 */ psq_st f3, 0x8(r29), 1, qr0 /* 800B392C 000AF76C E0 3D 80 00 */ psq_l f1, 0x0(r29), 1, qr0 /* 800B3930 000AF770 D0 01 00 1C */ stfs f0, 0x1c(r1) /* 800B3934 000AF774 E0 9D 00 04 */ psq_l f4, 0x4(r29), 0, qr0 /* 800B3938 000AF778 E0 03 00 04 */ psq_l f0, 0x4(r3), 0, qr0 /* 800B393C 000AF77C E0 BD 00 00 */ psq_l f5, 0x0(r29), 0, qr0 /* 800B3940 000AF780 10 84 00 32 */ ps_mul f4, f4, f0 /* 800B3944 000AF784 10 01 20 BA */ ps_madd f0, f1, f2, f4 /* 800B3948 000AF788 10 00 21 14 */ ps_sum0 f0, f0, f4, f4 /* 800B394C 000AF78C D0 01 00 40 */ stfs f0, 0x40(r1) /* 800B3950 000AF790 FC 00 00 18 */ frsp f0, f0 /* 800B3954 000AF794 10 25 00 18 */ ps_muls0 f1, f5, f0 /* 800B3958 000AF798 F0 24 00 00 */ psq_st f1, 0x0(r4), 0, qr0 /* 800B395C 000AF79C 10 23 00 18 */ ps_muls0 f1, f3, f0 /* 800B3960 000AF7A0 E0 04 00 00 */ psq_l f0, 0x0(r4), 0, qr0 /* 800B3964 000AF7A4 F0 24 80 08 */ psq_st f1, 0x8(r4), 1, qr0 /* 800B3968 000AF7A8 10 06 00 28 */ ps_sub f0, f6, f0 /* 800B396C 000AF7AC E0 C3 80 08 */ psq_l f6, 0x8(r3), 1, qr0 /* 800B3970 000AF7B0 F0 03 00 00 */ psq_st f0, 0x0(r3), 0, qr0 /* 800B3974 000AF7B4 10 06 08 28 */ ps_sub f0, f6, f1 /* 800B3978 000AF7B8 F0 03 80 08 */ psq_st f0, 0x8(r3), 1, qr0 /* 800B397C 000AF7BC 4B F7 DC 75 */ bl PSVECMag /* 800B3980 000AF7C0 D0 3C 00 08 */ stfs f1, 0x8(r28) /* 800B3984 000AF7C4 48 00 00 2C */ b lbl_800B39B0 .global lbl_800B3988 lbl_800B3988: /* 800B3988 000AF7C8 D0 44 00 04 */ stfs f2, 0x4(r4) /* 800B398C 000AF7CC C0 43 00 08 */ lfs f2, 0x8(r3) /* 800B3990 000AF7D0 C0 23 00 18 */ lfs f1, 0x18(r3) /* 800B3994 000AF7D4 C0 03 00 28 */ lfs f0, 0x28(r3) /* 800B3998 000AF7D8 38 61 00 14 */ addi r3, r1, 0x14 /* 800B399C 000AF7DC D0 41 00 14 */ stfs f2, 0x14(r1) /* 800B39A0 000AF7E0 D0 21 00 18 */ stfs f1, 0x18(r1) /* 800B39A4 000AF7E4 D0 01 00 1C */ stfs f0, 0x1c(r1) /* 800B39A8 000AF7E8 4B F7 DC 49 */ bl PSVECMag /* 800B39AC 000AF7EC D0 3C 00 08 */ stfs f1, 0x8(r28) .global lbl_800B39B0 lbl_800B39B0: /* 800B39B0 000AF7F0 39 61 00 60 */ addi r11, r1, 0x60 /* 800B39B4 000AF7F4 E3 E1 00 68 */ psq_l f31, 0x68(r1), 0, qr0 /* 800B39B8 000AF7F8 CB E1 00 60 */ lfd f31, 0x60(r1) /* 800B39BC 000AF7FC 4B F5 39 CD */ bl lbl_80007388 /* 800B39C0 000AF800 80 01 00 74 */ lwz r0, 0x74(r1) /* 800B39C4 000AF804 7C 08 03 A6 */ mtlr r0 /* 800B39C8 000AF808 38 21 00 70 */ addi r1, r1, 0x70 /* 800B39CC 000AF80C 4E 80 00 20 */ blr .global Normalize__Q24nw4r2efFPQ34nw4r4math4VEC3PCQ34nw4r4math4VEC3 Normalize__Q24nw4r2efFPQ34nw4r4math4VEC3PCQ34nw4r4math4VEC3: /* 800B39D0 000AF810 E0 64 00 00 */ psq_l f3, 0x0(r4), 0, qr0 /* 800B39D4 000AF814 C0 02 8B 68 */ lfs f0, "@6871"@sda21(r2) /* 800B39D8 000AF818 10 C3 00 F2 */ ps_mul f6, f3, f3 /* 800B39DC 000AF81C E0 84 80 08 */ psq_l f4, 0x8(r4), 1, qr0 /* 800B39E0 000AF820 EC 40 00 28 */ fsubs f2, f0, f0 /* 800B39E4 000AF824 C0 22 8B 6C */ lfs f1, "@6872"@sda21(r2) /* 800B39E8 000AF828 10 A4 31 3A */ ps_madd f5, f4, f4, f6 /* 800B39EC 000AF82C 10 A5 31 14 */ ps_sum0 f5, f5, f4, f6 /* 800B39F0 000AF830 FC 05 10 00 */ fcmpu cr0, f5, f2 /* 800B39F4 000AF834 41 82 00 30 */ beq lbl_800B3A24 /* 800B39F8 000AF838 FC 40 28 34 */ frsqrte f2, f5 /* 800B39FC 000AF83C EC C2 00 B2 */ fmuls f6, f2, f2 /* 800B3A00 000AF840 EC 02 00 32 */ fmuls f0, f2, f0 /* 800B3A04 000AF844 EC C6 09 7C */ fnmsubs f6, f6, f5, f1 /* 800B3A08 000AF848 EC 46 00 32 */ fmuls f2, f6, f0 /* 800B3A0C 000AF84C 10 63 00 98 */ ps_muls0 f3, f3, f2 /* 800B3A10 000AF850 10 84 00 98 */ ps_muls0 f4, f4, f2 /* 800B3A14 000AF854 F0 63 00 00 */ psq_st f3, 0x0(r3), 0, qr0 /* 800B3A18 000AF858 F0 83 80 08 */ psq_st f4, 0x8(r3), 1, qr0 /* 800B3A1C 000AF85C 38 60 00 01 */ li r3, 0x1 /* 800B3A20 000AF860 4E 80 00 20 */ blr .global lbl_800B3A24 lbl_800B3A24: /* 800B3A24 000AF864 F0 63 00 00 */ psq_st f3, 0x0(r3), 0, qr0 /* 800B3A28 000AF868 F0 83 80 08 */ psq_st f4, 0x8(r3), 1, qr0 /* 800B3A2C 000AF86C 38 60 00 00 */ li r3, 0x0 /* 800B3A30 000AF870 4E 80 00 20 */ blr /* 800B3A34 000AF874 00 00 00 00 */ .4byte 0x00000000 /* 800B3A38 000AF878 00 00 00 00 */ .4byte 0x00000000 /* 800B3A3C 000AF87C 00 00 00 00 */ .4byte 0x00000000 .global _PSSinCosRad__Q24nw4r2efFPff _PSSinCosRad__Q24nw4r2efFPff: /* 800B3A40 000AF880 C0 02 8B 48 */ lfs f0, "@6728"@sda21(r2) /* 800B3A44 000AF884 3C 80 80 41 */ lis r4, gSinCosTbl__Q34nw4r4math6detail@ha /* 800B3A48 000AF888 C0 42 8B 70 */ lfs f2, "@6879"@sda21(r2) /* 800B3A4C 000AF88C 38 84 8F 10 */ addi r4, r4, gSinCosTbl__Q34nw4r4math6detail@l /* 800B3A50 000AF890 EC 01 00 32 */ fmuls f0, f1, f0 /* 800B3A54 000AF894 FC 20 02 10 */ fabs f1, f0 /* 800B3A58 000AF898 F0 23 B0 00 */ psq_st f1, 0x0(r3), 1, qr3 /* 800B3A5C 000AF89C FC 01 10 00 */ fcmpu cr0, f1, f2 /* 800B3A60 000AF8A0 40 81 00 18 */ ble lbl_800B3A78 /* 800B3A64 000AF8A4 60 00 00 00 */ nop .global lbl_800B3A68 lbl_800B3A68: /* 800B3A68 000AF8A8 EC 21 10 28 */ fsubs f1, f1, f2 /* 800B3A6C 000AF8AC FC 01 10 00 */ fcmpu cr0, f1, f2 /* 800B3A70 000AF8B0 40 80 FF F8 */ bge lbl_800B3A68 /* 800B3A74 000AF8B4 F0 23 B0 00 */ psq_st f1, 0x0(r3), 1, qr3 .global lbl_800B3A78 lbl_800B3A78: /* 800B3A78 000AF8B8 A0 03 00 00 */ lhz r0, 0x0(r3) /* 800B3A7C 000AF8BC EC 82 10 28 */ fsubs f4, f2, f2 /* 800B3A80 000AF8C0 54 00 25 36 */ rlwinm r0, r0, 4, 20, 27 /* 800B3A84 000AF8C4 7C 84 02 14 */ add r4, r4, r0 /* 800B3A88 000AF8C8 E0 43 B0 00 */ psq_l f2, 0x0(r3), 1, qr3 /* 800B3A8C 000AF8CC FC 00 20 00 */ fcmpu cr0, f0, f4 /* 800B3A90 000AF8D0 E0 64 00 00 */ psq_l f3, 0x0(r4), 0, qr0 /* 800B3A94 000AF8D4 EC 41 10 28 */ fsubs f2, f1, f2 /* 800B3A98 000AF8D8 E0 04 00 08 */ psq_l f0, 0x8(r4), 0, qr0 /* 800B3A9C 000AF8DC 10 20 18 9C */ ps_madds0 f1, f0, f2, f3 /* 800B3AA0 000AF8E0 40 80 00 0C */ bge lbl_800B3AAC /* 800B3AA4 000AF8E4 10 00 08 50 */ ps_neg f0, f1 /* 800B3AA8 000AF8E8 10 20 0C 60 */ ps_merge01 f1, f0, f1 .global lbl_800B3AAC lbl_800B3AAC: /* 800B3AAC 000AF8EC F0 23 00 00 */ psq_st f1, 0x0(r3), 0, qr0 /* 800B3AB0 000AF8F0 4E 80 00 20 */ blr /* 800B3AB4 000AF8F4 00 00 00 00 */ .4byte 0x00000000 /* 800B3AB8 000AF8F8 00 00 00 00 */ .4byte 0x00000000 /* 800B3ABC 000AF8FC 00 00 00 00 */ .4byte 0x00000000 .global PSSinCosRad__Q24nw4r2efFPfPff PSSinCosRad__Q24nw4r2efFPfPff: /* 800B3AC0 000AF900 C0 02 8B 48 */ lfs f0, "@6728"@sda21(r2) /* 800B3AC4 000AF904 3C A0 80 41 */ lis r5, gSinCosTbl__Q34nw4r4math6detail@ha /* 800B3AC8 000AF908 C0 42 8B 70 */ lfs f2, "@6879"@sda21(r2) /* 800B3ACC 000AF90C 38 A5 8F 10 */ addi r5, r5, gSinCosTbl__Q34nw4r4math6detail@l /* 800B3AD0 000AF910 EC 01 00 32 */ fmuls f0, f1, f0 /* 800B3AD4 000AF914 FC 20 02 10 */ fabs f1, f0 /* 800B3AD8 000AF918 F0 23 B0 00 */ psq_st f1, 0x0(r3), 1, qr3 /* 800B3ADC 000AF91C FC 01 10 00 */ fcmpu cr0, f1, f2 /* 800B3AE0 000AF920 40 81 00 18 */ ble lbl_800B3AF8 /* 800B3AE4 000AF924 60 00 00 00 */ nop .global lbl_800B3AE8 lbl_800B3AE8: /* 800B3AE8 000AF928 EC 21 10 28 */ fsubs f1, f1, f2 /* 800B3AEC 000AF92C FC 01 10 00 */ fcmpu cr0, f1, f2 /* 800B3AF0 000AF930 40 80 FF F8 */ bge lbl_800B3AE8 /* 800B3AF4 000AF934 F0 23 B0 00 */ psq_st f1, 0x0(r3), 1, qr3 .global lbl_800B3AF8 lbl_800B3AF8: /* 800B3AF8 000AF938 A0 03 00 00 */ lhz r0, 0x0(r3) /* 800B3AFC 000AF93C EC 82 10 28 */ fsubs f4, f2, f2 /* 800B3B00 000AF940 54 00 25 36 */ rlwinm r0, r0, 4, 20, 27 /* 800B3B04 000AF944 7C A5 02 14 */ add r5, r5, r0 /* 800B3B08 000AF948 E0 43 B0 00 */ psq_l f2, 0x0(r3), 1, qr3 /* 800B3B0C 000AF94C FC 00 20 00 */ fcmpu cr0, f0, f4 /* 800B3B10 000AF950 E0 65 00 00 */ psq_l f3, 0x0(r5), 0, qr0 /* 800B3B14 000AF954 EC 41 10 28 */ fsubs f2, f1, f2 /* 800B3B18 000AF958 E0 05 00 08 */ psq_l f0, 0x8(r5), 0, qr0 /* 800B3B1C 000AF95C 10 00 18 9C */ ps_madds0 f0, f0, f2, f3 /* 800B3B20 000AF960 10 40 04 A0 */ ps_merge10 f2, f0, f0 /* 800B3B24 000AF964 F0 44 80 00 */ psq_st f2, 0x0(r4), 1, qr0 /* 800B3B28 000AF968 40 80 00 08 */ bge lbl_800B3B30 /* 800B3B2C 000AF96C 10 00 00 50 */ ps_neg f0, f0 .global lbl_800B3B30 lbl_800B3B30: /* 800B3B30 000AF970 F0 03 80 00 */ psq_st f0, 0x0(r3), 1, qr0 /* 800B3B34 000AF974 4E 80 00 20 */ blr /* 800B3B38 000AF978 00 00 00 00 */ .4byte 0x00000000 /* 800B3B3C 000AF97C 00 00 00 00 */ .4byte 0x00000000 .global Rotation2VecY__Q24nw4r2efFRCQ34nw4r4math4VEC3PQ34nw4r4math4VEC3 Rotation2VecY__Q24nw4r2efFRCQ34nw4r4math4VEC3PQ34nw4r4math4VEC3: /* 800B3B40 000AF980 C0 03 00 00 */ lfs f0, 0x0(r3) /* 800B3B44 000AF984 38 02 8B 40 */ addi r0, r2, "@6727"@sda21 /* 800B3B48 000AF988 C0 23 00 04 */ lfs f1, 0x4(r3) /* 800B3B4C 000AF98C 3C A0 80 41 */ lis r5, gSinCosTbl__Q34nw4r4math6detail@ha /* 800B3B50 000AF990 10 40 00 0C */ psq_lx f2, r0, r0, 0, qr0 /* 800B3B54 000AF994 38 A5 8F 10 */ addi r5, r5, gSinCosTbl__Q34nw4r4math6detail@l /* 800B3B58 000AF998 10 C0 0C 20 */ ps_merge00 f6, f0, f1 /* 800B3B5C 000AF99C C0 62 8B 48 */ lfs f3, "@6728"@sda21(r2) /* 800B3B60 000AF9A0 10 42 14 20 */ ps_merge00 f2, f2, f2 /* 800B3B64 000AF9A4 94 21 FF F0 */ stwu r1, -0x10(r1) /* 800B3B68 000AF9A8 C0 03 00 08 */ lfs f0, 0x8(r3) /* 800B3B6C 000AF9AC 10 C6 00 D8 */ ps_muls0 f6, f6, f3 /* 800B3B70 000AF9B0 10 20 10 50 */ ps_neg f1, f2 /* 800B3B74 000AF9B4 38 E1 00 08 */ addi r7, r1, 0x8 /* 800B3B78 000AF9B8 10 82 10 28 */ ps_sub f4, f2, f2 /* 800B3B7C 000AF9BC 10 A0 32 10 */ ps_abs f5, f6 /* 800B3B80 000AF9C0 10 05 10 00 */ ps_cmpu0 cr0, f5, f2 /* 800B3B84 000AF9C4 40 81 00 10 */ ble lbl_800B3B94 .global lbl_800B3B88 lbl_800B3B88: /* 800B3B88 000AF9C8 10 A5 09 54 */ ps_sum0 f5, f5, f5, f1 /* 800B3B8C 000AF9CC 10 05 10 00 */ ps_cmpu0 cr0, f5, f2 /* 800B3B90 000AF9D0 40 80 FF F8 */ bge lbl_800B3B88 .global lbl_800B3B94 lbl_800B3B94: /* 800B3B94 000AF9D4 10 05 10 80 */ ps_cmpu1 cr0, f5, f2 /* 800B3B98 000AF9D8 40 81 00 18 */ ble lbl_800B3BB0 /* 800B3B9C 000AF9DC 10 A5 2C A0 */ ps_merge10 f5, f5, f5 .global lbl_800B3BA0 lbl_800B3BA0: /* 800B3BA0 000AF9E0 10 A5 09 54 */ ps_sum0 f5, f5, f5, f1 /* 800B3BA4 000AF9E4 10 05 10 00 */ ps_cmpu0 cr0, f5, f2 /* 800B3BA8 000AF9E8 40 80 FF F8 */ bge lbl_800B3BA0 /* 800B3BAC 000AF9EC 10 A5 2C A0 */ ps_merge10 f5, f5, f5 .global lbl_800B3BB0 lbl_800B3BB0: /* 800B3BB0 000AF9F0 F0 A7 30 00 */ psq_st f5, 0x0(r7), 0, qr3 /* 800B3BB4 000AF9F4 EC E0 00 F2 */ fmuls f7, f0, f3 /* 800B3BB8 000AF9F8 E1 07 30 00 */ psq_l f8, 0x0(r7), 0, qr3 /* 800B3BBC 000AF9FC FC 60 3A 10 */ fabs f3, f7 /* 800B3BC0 000AFA00 80 01 00 08 */ lwz r0, 0x8(r1) /* 800B3BC4 000AFA04 FC 03 10 00 */ fcmpu cr0, f3, f2 /* 800B3BC8 000AFA08 40 81 00 14 */ ble lbl_800B3BDC /* 800B3BCC 000AFA0C 60 00 00 00 */ nop .global lbl_800B3BD0 lbl_800B3BD0: /* 800B3BD0 000AFA10 EC 63 10 28 */ fsubs f3, f3, f2 /* 800B3BD4 000AFA14 FC 03 10 00 */ fcmpu cr0, f3, f2 /* 800B3BD8 000AFA18 40 80 FF F8 */ bge lbl_800B3BD0 .global lbl_800B3BDC lbl_800B3BDC: /* 800B3BDC 000AFA1C F0 67 B0 00 */ psq_st f3, 0x0(r7), 1, qr3 /* 800B3BE0 000AFA20 54 03 A5 36 */ rlwinm r3, r0, 20, 20, 27 /* 800B3BE4 000AFA24 7C 65 1A 14 */ add r3, r5, r3 /* 800B3BE8 000AFA28 11 05 40 28 */ ps_sub f8, f5, f8 /* 800B3BEC 000AFA2C E0 43 00 00 */ psq_l f2, 0x0(r3), 0, qr0 /* 800B3BF0 000AFA30 54 06 25 36 */ rlwinm r6, r0, 4, 20, 27 /* 800B3BF4 000AFA34 E0 A3 00 08 */ psq_l f5, 0x8(r3), 0, qr0 /* 800B3BF8 000AFA38 10 06 20 00 */ ps_cmpu0 cr0, f6, f4 /* 800B3BFC 000AFA3C 7C C5 32 14 */ add r6, r5, r6 /* 800B3C00 000AFA40 10 05 12 1C */ ps_madds0 f0, f5, f8, f2 /* 800B3C04 000AFA44 E0 46 00 00 */ psq_l f2, 0x0(r6), 0, qr0 /* 800B3C08 000AFA48 E0 A6 00 08 */ psq_l f5, 0x8(r6), 0, qr0 /* 800B3C0C 000AFA4C A0 01 00 08 */ lhz r0, 0x8(r1) /* 800B3C10 000AFA50 40 80 00 0C */ bge lbl_800B3C1C /* 800B3C14 000AFA54 11 20 00 50 */ ps_neg f9, f0 /* 800B3C18 000AFA58 10 09 04 60 */ ps_merge01 f0, f9, f0 .global lbl_800B3C1C lbl_800B3C1C: /* 800B3C1C 000AFA5C 10 25 12 1E */ ps_madds1 f1, f5, f8, f2 /* 800B3C20 000AFA60 E1 07 B0 00 */ psq_l f8, 0x0(r7), 1, qr3 /* 800B3C24 000AFA64 54 00 25 36 */ rlwinm r0, r0, 4, 20, 27 /* 800B3C28 000AFA68 10 06 20 80 */ ps_cmpu1 cr0, f6, f4 /* 800B3C2C 000AFA6C 7C 65 02 14 */ add r3, r5, r0 /* 800B3C30 000AFA70 ED 03 40 28 */ fsubs f8, f3, f8 /* 800B3C34 000AFA74 E0 43 00 00 */ psq_l f2, 0x0(r3), 0, qr0 /* 800B3C38 000AFA78 E0 A3 00 08 */ psq_l f5, 0x8(r3), 0, qr0 /* 800B3C3C 000AFA7C 40 80 00 0C */ bge lbl_800B3C48 /* 800B3C40 000AFA80 11 20 08 50 */ ps_neg f9, f1 /* 800B3C44 000AFA84 10 29 0C 60 */ ps_merge01 f1, f9, f1 .global lbl_800B3C48 lbl_800B3C48: /* 800B3C48 000AFA88 FC 07 20 00 */ fcmpu cr0, f7, f4 /* 800B3C4C 000AFA8C 10 45 12 1C */ ps_madds0 f2, f5, f8, f2 /* 800B3C50 000AFA90 40 80 00 0C */ bge lbl_800B3C5C /* 800B3C54 000AFA94 11 20 10 50 */ ps_neg f9, f2 /* 800B3C58 000AFA98 10 49 14 60 */ ps_merge01 f2, f9, f2 .global lbl_800B3C5C lbl_800B3C5C: /* 800B3C5C 000AFA9C 10 62 00 1A */ ps_muls1 f3, f2, f0 /* 800B3C60 000AFAA0 7C 83 23 78 */ mr r3, r4 /* 800B3C64 000AFAA4 10 21 00 18 */ ps_muls0 f1, f1, f0 /* 800B3C68 000AFAA8 10 42 14 A0 */ ps_merge10 f2, f2, f2 /* 800B3C6C 000AFAAC 10 00 18 50 */ ps_neg f0, f3 /* 800B3C70 000AFAB0 10 60 1C 60 */ ps_merge01 f3, f0, f3 /* 800B3C74 000AFAB4 10 42 18 5C */ ps_madds0 f2, f2, f1, f3 /* 800B3C78 000AFAB8 10 21 0C A0 */ ps_merge10 f1, f1, f1 /* 800B3C7C 000AFABC F0 44 00 00 */ psq_st f2, 0x0(r4), 0, qr0 /* 800B3C80 000AFAC0 F0 24 80 08 */ psq_st f1, 0x8(r4), 1, qr0 /* 800B3C84 000AFAC4 38 21 00 10 */ addi r1, r1, 0x10 /* 800B3C88 000AFAC8 4E 80 00 20 */ blr /* 800B3C8C 000AFACC 00 00 00 00 */ .4byte 0x00000000 .global PSMTX34RotXYZRad__Q24nw4r2efFPQ34nw4r4math5MTX34fff PSMTX34RotXYZRad__Q24nw4r2efFPQ34nw4r4math5MTX34fff: /* 800B3C90 000AFAD0 10 C1 14 20 */ ps_merge00 f6, f1, f2 /* 800B3C94 000AFAD4 C0 42 8B 48 */ lfs f2, "@6728"@sda21(r2) /* 800B3C98 000AFAD8 38 02 8B 40 */ addi r0, r2, "@6727"@sda21 /* 800B3C9C 000AFADC 94 21 FF F0 */ stwu r1, -0x10(r1) /* 800B3CA0 000AFAE0 10 00 00 0C */ psq_lx f0, r0, r0, 0, qr0 /* 800B3CA4 000AFAE4 3C 80 80 41 */ lis r4, gSinCosTbl__Q34nw4r4math6detail@ha /* 800B3CA8 000AFAE8 10 C6 00 98 */ ps_muls0 f6, f6, f2 /* 800B3CAC 000AFAEC 38 84 8F 10 */ addi r4, r4, gSinCosTbl__Q34nw4r4math6detail@l /* 800B3CB0 000AFAF0 10 00 04 20 */ ps_merge00 f0, f0, f0 /* 800B3CB4 000AFAF4 38 E1 00 08 */ addi r7, r1, 0x8 /* 800B3CB8 000AFAF8 10 A0 32 10 */ ps_abs f5, f6 /* 800B3CBC 000AFAFC 10 20 00 50 */ ps_neg f1, f0 /* 800B3CC0 000AFB00 10 80 00 28 */ ps_sub f4, f0, f0 /* 800B3CC4 000AFB04 10 05 00 00 */ ps_cmpu0 cr0, f5, f0 /* 800B3CC8 000AFB08 40 81 00 14 */ ble lbl_800B3CDC /* 800B3CCC 000AFB0C 60 00 00 00 */ nop .global lbl_800B3CD0 lbl_800B3CD0: /* 800B3CD0 000AFB10 10 A5 09 54 */ ps_sum0 f5, f5, f5, f1 /* 800B3CD4 000AFB14 10 05 00 00 */ ps_cmpu0 cr0, f5, f0 /* 800B3CD8 000AFB18 40 80 FF F8 */ bge lbl_800B3CD0 .global lbl_800B3CDC lbl_800B3CDC: /* 800B3CDC 000AFB1C 10 05 00 80 */ ps_cmpu1 cr0, f5, f0 /* 800B3CE0 000AFB20 40 81 00 18 */ ble lbl_800B3CF8 /* 800B3CE4 000AFB24 10 A5 2C A0 */ ps_merge10 f5, f5, f5 .global lbl_800B3CE8 lbl_800B3CE8: /* 800B3CE8 000AFB28 10 A5 09 54 */ ps_sum0 f5, f5, f5, f1 /* 800B3CEC 000AFB2C 10 05 00 00 */ ps_cmpu0 cr0, f5, f0 /* 800B3CF0 000AFB30 40 80 FF F8 */ bge lbl_800B3CE8 /* 800B3CF4 000AFB34 10 A5 2C A0 */ ps_merge10 f5, f5, f5 .global lbl_800B3CF8 lbl_800B3CF8: /* 800B3CF8 000AFB38 F0 A7 30 00 */ psq_st f5, 0x0(r7), 0, qr3 /* 800B3CFC 000AFB3C EC 63 00 B2 */ fmuls f3, f3, f2 /* 800B3D00 000AFB40 E0 E7 30 00 */ psq_l f7, 0x0(r7), 0, qr3 /* 800B3D04 000AFB44 FC 40 1A 10 */ fabs f2, f3 /* 800B3D08 000AFB48 80 01 00 08 */ lwz r0, 0x8(r1) /* 800B3D0C 000AFB4C FC 02 00 00 */ fcmpu cr0, f2, f0 /* 800B3D10 000AFB50 40 81 00 14 */ ble lbl_800B3D24 /* 800B3D14 000AFB54 60 00 00 00 */ nop .global lbl_800B3D18 lbl_800B3D18: /* 800B3D18 000AFB58 EC 42 00 28 */ fsubs f2, f2, f0 /* 800B3D1C 000AFB5C FC 02 00 00 */ fcmpu cr0, f2, f0 /* 800B3D20 000AFB60 40 80 FF F8 */ bge lbl_800B3D18 .global lbl_800B3D24 lbl_800B3D24: /* 800B3D24 000AFB64 F0 47 B0 00 */ psq_st f2, 0x0(r7), 1, qr3 /* 800B3D28 000AFB68 54 05 A5 36 */ rlwinm r5, r0, 20, 20, 27 /* 800B3D2C 000AFB6C 7C A4 2A 14 */ add r5, r4, r5 /* 800B3D30 000AFB70 10 E5 38 28 */ ps_sub f7, f5, f7 /* 800B3D34 000AFB74 E0 A5 00 00 */ psq_l f5, 0x0(r5), 0, qr0 /* 800B3D38 000AFB78 54 06 25 36 */ rlwinm r6, r0, 4, 20, 27 /* 800B3D3C 000AFB7C E1 05 00 08 */ psq_l f8, 0x8(r5), 0, qr0 /* 800B3D40 000AFB80 10 06 20 00 */ ps_cmpu0 cr0, f6, f4 /* 800B3D44 000AFB84 7C C4 32 14 */ add r6, r4, r6 /* 800B3D48 000AFB88 10 08 29 DC */ ps_madds0 f0, f8, f7, f5 /* 800B3D4C 000AFB8C E0 A6 00 00 */ psq_l f5, 0x0(r6), 0, qr0 /* 800B3D50 000AFB90 E1 06 00 08 */ psq_l f8, 0x8(r6), 0, qr0 /* 800B3D54 000AFB94 A0 01 00 08 */ lhz r0, 0x8(r1) /* 800B3D58 000AFB98 40 80 00 0C */ bge lbl_800B3D64 /* 800B3D5C 000AFB9C 11 20 00 50 */ ps_neg f9, f0 /* 800B3D60 000AFBA0 10 09 04 60 */ ps_merge01 f0, f9, f0 .global lbl_800B3D64 lbl_800B3D64: /* 800B3D64 000AFBA4 10 28 29 DE */ ps_madds1 f1, f8, f7, f5 /* 800B3D68 000AFBA8 E0 E7 B0 00 */ psq_l f7, 0x0(r7), 1, qr3 /* 800B3D6C 000AFBAC 54 00 25 36 */ rlwinm r0, r0, 4, 20, 27 /* 800B3D70 000AFBB0 10 06 20 80 */ ps_cmpu1 cr0, f6, f4 /* 800B3D74 000AFBB4 7C A4 02 14 */ add r5, r4, r0 /* 800B3D78 000AFBB8 EC E2 38 28 */ fsubs f7, f2, f7 /* 800B3D7C 000AFBBC E0 A5 00 00 */ psq_l f5, 0x0(r5), 0, qr0 /* 800B3D80 000AFBC0 E1 05 00 08 */ psq_l f8, 0x8(r5), 0, qr0 /* 800B3D84 000AFBC4 40 80 00 0C */ bge lbl_800B3D90 /* 800B3D88 000AFBC8 11 20 08 50 */ ps_neg f9, f1 /* 800B3D8C 000AFBCC 10 29 0C 60 */ ps_merge01 f1, f9, f1 .global lbl_800B3D90 lbl_800B3D90: /* 800B3D90 000AFBD0 FC 03 20 00 */ fcmpu cr0, f3, f4 /* 800B3D94 000AFBD4 10 48 29 DC */ ps_madds0 f2, f8, f7, f5 /* 800B3D98 000AFBD8 40 80 00 0C */ bge lbl_800B3DA4 /* 800B3D9C 000AFBDC 11 20 10 50 */ ps_neg f9, f2 /* 800B3DA0 000AFBE0 10 49 14 60 */ ps_merge01 f2, f9, f2 .global lbl_800B3DA4 lbl_800B3DA4: /* 800B3DA4 000AFBE4 10 60 00 50 */ ps_neg f3, f0 /* 800B3DA8 000AFBE8 10 A2 00 5A */ ps_muls1 f5, f2, f1 /* 800B3DAC 000AFBEC 10 E0 00 28 */ ps_sub f7, f0, f0 /* 800B3DB0 000AFBF0 10 63 04 A0 */ ps_merge10 f3, f3, f0 /* 800B3DB4 000AFBF4 10 C5 2C A0 */ ps_merge10 f6, f5, f5 /* 800B3DB8 000AFBF8 F0 E3 80 2C */ psq_st f7, 0x2c(r3), 1, qr0 /* 800B3DBC 000AFBFC 10 80 00 98 */ ps_muls0 f4, f0, f2 /* 800B3DC0 000AFC00 F0 C3 80 00 */ psq_st f6, 0x0(r3), 1, qr0 /* 800B3DC4 000AFC04 10 C0 00 9A */ ps_muls1 f6, f0, f2 /* 800B3DC8 000AFC08 11 03 00 98 */ ps_muls0 f8, f3, f2 /* 800B3DCC 000AFC0C 10 43 00 9A */ ps_muls1 f2, f3, f2 /* 800B3DD0 000AFC10 10 C6 40 5C */ ps_madds0 f6, f6, f1, f8 /* 800B3DD4 000AFC14 10 40 10 50 */ ps_neg f2, f2 /* 800B3DD8 000AFC18 F0 C3 00 04 */ psq_st f6, 0x4(r3), 0, qr0 /* 800B3DDC 000AFC1C 10 C7 2C 20 */ ps_merge00 f6, f7, f5 /* 800B3DE0 000AFC20 F0 C3 00 0C */ psq_st f6, 0xc(r3), 0, qr0 /* 800B3DE4 000AFC24 10 C4 10 5C */ ps_madds0 f6, f4, f1, f2 /* 800B3DE8 000AFC28 F0 C3 00 14 */ psq_st f6, 0x14(r3), 0, qr0 /* 800B3DEC 000AFC2C 10 C0 08 50 */ ps_neg f6, f1 /* 800B3DF0 000AFC30 10 C7 34 20 */ ps_merge00 f6, f7, f6 /* 800B3DF4 000AFC34 F0 C3 00 1C */ psq_st f6, 0x1c(r3), 0, qr0 /* 800B3DF8 000AFC38 10 C0 00 5A */ ps_muls1 f6, f0, f1 /* 800B3DFC 000AFC3C F0 C3 00 24 */ psq_st f6, 0x24(r3), 0, qr0 /* 800B3E00 000AFC40 38 21 00 10 */ addi r1, r1, 0x10 /* 800B3E04 000AFC44 4E 80 00 20 */ blr /* 800B3E08 000AFC48 00 00 00 00 */ .4byte 0x00000000 /* 800B3E0C 000AFC4C 00 00 00 00 */ .4byte 0x00000000 .global MTX34ScaleNonZero__Q24nw4r2efFPQ34nw4r4math5MTX34PCQ34nw4r4math5MTX34PCQ34nw4r4math4VEC3 MTX34ScaleNonZero__Q24nw4r2efFPQ34nw4r4math5MTX34PCQ34nw4r4math5MTX34PCQ34nw4r4math4VEC3: /* 800B3E10 000AFC50 E0 05 00 00 */ psq_l f0, 0x0(r5), 0, qr0 /* 800B3E14 000AFC54 C1 02 8B 74 */ lfs f8, "@6916"@sda21(r2) /* 800B3E18 000AFC58 10 C0 00 28 */ ps_sub f6, f0, f0 /* 800B3E1C 000AFC5C E0 25 80 08 */ psq_l f1, 0x8(r5), 1, qr0 /* 800B3E20 000AFC60 E0 44 00 00 */ psq_l f2, 0x0(r4), 0, qr0 /* 800B3E24 000AFC64 E0 64 00 08 */ psq_l f3, 0x8(r4), 0, qr0 /* 800B3E28 000AFC68 10 00 30 00 */ ps_cmpu0 cr0, f0, f6 /* 800B3E2C 000AFC6C 40 82 00 08 */ bne lbl_800B3E34 /* 800B3E30 000AFC70 10 08 04 60 */ ps_merge01 f0, f8, f0 .global lbl_800B3E34 lbl_800B3E34: /* 800B3E34 000AFC74 10 00 30 80 */ ps_cmpu1 cr0, f0, f6 /* 800B3E38 000AFC78 E0 84 00 10 */ psq_l f4, 0x10(r4), 0, qr0 /* 800B3E3C 000AFC7C E0 A4 00 18 */ psq_l f5, 0x18(r4), 0, qr0 /* 800B3E40 000AFC80 40 82 00 08 */ bne lbl_800B3E48 /* 800B3E44 000AFC84 10 00 44 20 */ ps_merge00 f0, f0, f8 .global lbl_800B3E48 lbl_800B3E48: /* 800B3E48 000AFC88 10 01 30 00 */ ps_cmpu0 cr0, f1, f6 /* 800B3E4C 000AFC8C E0 C4 00 20 */ psq_l f6, 0x20(r4), 0, qr0 /* 800B3E50 000AFC90 E0 E4 00 28 */ psq_l f7, 0x28(r4), 0, qr0 /* 800B3E54 000AFC94 40 82 00 08 */ bne lbl_800B3E5C /* 800B3E58 000AFC98 10 28 0C 60 */ ps_merge01 f1, f8, f1 .global lbl_800B3E5C lbl_800B3E5C: /* 800B3E5C 000AFC9C 10 42 00 32 */ ps_mul f2, f2, f0 /* 800B3E60 000AFCA0 10 84 00 32 */ ps_mul f4, f4, f0 /* 800B3E64 000AFCA4 10 C6 00 32 */ ps_mul f6, f6, f0 /* 800B3E68 000AFCA8 F0 43 00 00 */ psq_st f2, 0x0(r3), 0, qr0 /* 800B3E6C 000AFCAC 10 63 00 72 */ ps_mul f3, f3, f1 /* 800B3E70 000AFCB0 10 A5 00 72 */ ps_mul f5, f5, f1 /* 800B3E74 000AFCB4 F0 83 00 10 */ psq_st f4, 0x10(r3), 0, qr0 /* 800B3E78 000AFCB8 10 E7 00 72 */ ps_mul f7, f7, f1 /* 800B3E7C 000AFCBC F0 63 00 08 */ psq_st f3, 0x8(r3), 0, qr0 /* 800B3E80 000AFCC0 F0 C3 00 20 */ psq_st f6, 0x20(r3), 0, qr0 /* 800B3E84 000AFCC4 F0 A3 00 18 */ psq_st f5, 0x18(r3), 0, qr0 /* 800B3E88 000AFCC8 F0 E3 00 28 */ psq_st f7, 0x28(r3), 0, qr0 /* 800B3E8C 000AFCCC 4E 80 00 20 */ blr .global MTX34ScaleNonZero__Q24nw4r2efFPQ34nw4r4math5MTX34PCQ34nw4r4math4VEC3PCQ34nw4r4math5MTX34 MTX34ScaleNonZero__Q24nw4r2efFPQ34nw4r4math5MTX34PCQ34nw4r4math4VEC3PCQ34nw4r4math5MTX34: /* 800B3E90 000AFCD0 3C C0 80 56 */ lis r6, EMITTER_ZERO_SCALE__Q24nw4r2ef@ha /* 800B3E94 000AFCD4 C1 24 00 00 */ lfs f9, 0x0(r4) /* 800B3E98 000AFCD8 C1 86 EA FC */ lfs f12, EMITTER_ZERO_SCALE__Q24nw4r2ef@l(r6) /* 800B3E9C 000AFCDC C1 44 00 04 */ lfs f10, 0x4(r4) /* 800B3EA0 000AFCE0 ED AC 60 28 */ fsubs f13, f12, f12 /* 800B3EA4 000AFCE4 C1 64 00 08 */ lfs f11, 0x8(r4) /* 800B3EA8 000AFCE8 E0 85 00 00 */ psq_l f4, 0x0(r5), 0, qr0 /* 800B3EAC 000AFCEC E0 A5 00 08 */ psq_l f5, 0x8(r5), 0, qr0 /* 800B3EB0 000AFCF0 FC 09 68 00 */ fcmpu cr0, f9, f13 /* 800B3EB4 000AFCF4 40 82 00 08 */ bne lbl_800B3EBC /* 800B3EB8 000AFCF8 FD 20 60 90 */ fmr f9, f12 .global lbl_800B3EBC lbl_800B3EBC: /* 800B3EBC 000AFCFC FC 0A 68 00 */ fcmpu cr0, f10, f13 /* 800B3EC0 000AFD00 E0 C5 00 10 */ psq_l f6, 0x10(r5), 0, qr0 /* 800B3EC4 000AFD04 E0 E5 00 18 */ psq_l f7, 0x18(r5), 0, qr0 /* 800B3EC8 000AFD08 40 82 00 08 */ bne lbl_800B3ED0 /* 800B3ECC 000AFD0C FD 40 60 90 */ fmr f10, f12 .global lbl_800B3ED0 lbl_800B3ED0: /* 800B3ED0 000AFD10 FC 0B 68 00 */ fcmpu cr0, f11, f13 /* 800B3ED4 000AFD14 E1 05 00 20 */ psq_l f8, 0x20(r5), 0, qr0 /* 800B3ED8 000AFD18 E0 45 00 28 */ psq_l f2, 0x28(r5), 0, qr0 /* 800B3EDC 000AFD1C 40 82 00 08 */ bne lbl_800B3EE4 /* 800B3EE0 000AFD20 FD 60 60 90 */ fmr f11, f12 .global lbl_800B3EE4 lbl_800B3EE4: /* 800B3EE4 000AFD24 10 84 02 58 */ ps_muls0 f4, f4, f9 /* 800B3EE8 000AFD28 10 A5 02 58 */ ps_muls0 f5, f5, f9 /* 800B3EEC 000AFD2C 10 C6 02 98 */ ps_muls0 f6, f6, f10 /* 800B3EF0 000AFD30 F0 83 00 00 */ psq_st f4, 0x0(r3), 0, qr0 /* 800B3EF4 000AFD34 10 E7 02 98 */ ps_muls0 f7, f7, f10 /* 800B3EF8 000AFD38 11 08 02 D8 */ ps_muls0 f8, f8, f11 /* 800B3EFC 000AFD3C F0 A3 00 08 */ psq_st f5, 0x8(r3), 0, qr0 /* 800B3F00 000AFD40 10 42 02 D8 */ ps_muls0 f2, f2, f11 /* 800B3F04 000AFD44 F0 C3 00 10 */ psq_st f6, 0x10(r3), 0, qr0 /* 800B3F08 000AFD48 F0 E3 00 18 */ psq_st f7, 0x18(r3), 0, qr0 /* 800B3F0C 000AFD4C F1 03 00 20 */ psq_st f8, 0x20(r3), 0, qr0 /* 800B3F10 000AFD50 F0 43 00 28 */ psq_st f2, 0x28(r3), 0, qr0 /* 800B3F14 000AFD54 4E 80 00 20 */ blr /* 800B3F18 000AFD58 00 00 00 00 */ .4byte 0x00000000 /* 800B3F1C 000AFD5C 00 00 00 00 */ .4byte 0x00000000 .global MTX34ScaleInv__Q24nw4r2efFPQ34nw4r4math5MTX34PCQ34nw4r4math5MTX34PCQ34nw4r4math4VEC3 MTX34ScaleInv__Q24nw4r2efFPQ34nw4r4math5MTX34PCQ34nw4r4math5MTX34PCQ34nw4r4math4VEC3: /* 800B3F20 000AFD60 94 21 FF E0 */ stwu r1, -0x20(r1) /* 800B3F24 000AFD64 7C 08 02 A6 */ mflr r0 /* 800B3F28 000AFD68 C0 22 8B 54 */ lfs f1, "@6745"@sda21(r2) /* 800B3F2C 000AFD6C C0 05 00 00 */ lfs f0, 0x0(r5) /* 800B3F30 000AFD70 90 01 00 24 */ stw r0, 0x24(r1) /* 800B3F34 000AFD74 FC 01 00 00 */ fcmpu cr0, f1, f0 /* 800B3F38 000AFD78 41 82 00 18 */ beq lbl_800B3F50 /* 800B3F3C 000AFD7C EC 60 00 30 */ fres f3, f0 /* 800B3F40 000AFD80 10 43 18 2A */ ps_add f2, f3, f3 /* 800B3F44 000AFD84 10 23 00 F2 */ ps_mul f1, f3, f3 /* 800B3F48 000AFD88 10 60 10 7C */ ps_nmsub f3, f0, f1, f2 /* 800B3F4C 000AFD8C 48 00 00 08 */ b lbl_800B3F54 .global lbl_800B3F50 lbl_800B3F50: /* 800B3F50 000AFD90 C0 62 8B 78 */ lfs f3, "@6934"@sda21(r2) .global lbl_800B3F54 lbl_800B3F54: /* 800B3F54 000AFD94 C0 22 8B 54 */ lfs f1, "@6745"@sda21(r2) /* 800B3F58 000AFD98 C0 05 00 04 */ lfs f0, 0x4(r5) /* 800B3F5C 000AFD9C D0 61 00 08 */ stfs f3, 0x8(r1) /* 800B3F60 000AFDA0 FC 01 00 00 */ fcmpu cr0, f1, f0 /* 800B3F64 000AFDA4 41 82 00 18 */ beq lbl_800B3F7C /* 800B3F68 000AFDA8 EC 60 00 30 */ fres f3, f0 /* 800B3F6C 000AFDAC 10 43 18 2A */ ps_add f2, f3, f3 /* 800B3F70 000AFDB0 10 23 00 F2 */ ps_mul f1, f3, f3 /* 800B3F74 000AFDB4 10 60 10 7C */ ps_nmsub f3, f0, f1, f2 /* 800B3F78 000AFDB8 48 00 00 08 */ b lbl_800B3F80 .global lbl_800B3F7C lbl_800B3F7C: /* 800B3F7C 000AFDBC C0 62 8B 78 */ lfs f3, "@6934"@sda21(r2) .global lbl_800B3F80 lbl_800B3F80: /* 800B3F80 000AFDC0 C0 22 8B 54 */ lfs f1, "@6745"@sda21(r2) /* 800B3F84 000AFDC4 C0 05 00 08 */ lfs f0, 0x8(r5) /* 800B3F88 000AFDC8 D0 61 00 0C */ stfs f3, 0xc(r1) /* 800B3F8C 000AFDCC FC 01 00 00 */ fcmpu cr0, f1, f0 /* 800B3F90 000AFDD0 41 82 00 18 */ beq lbl_800B3FA8 /* 800B3F94 000AFDD4 EC 20 00 30 */ fres f1, f0 /* 800B3F98 000AFDD8 10 41 08 2A */ ps_add f2, f1, f1 /* 800B3F9C 000AFDDC 10 21 00 72 */ ps_mul f1, f1, f1 /* 800B3FA0 000AFDE0 10 20 10 7C */ ps_nmsub f1, f0, f1, f2 /* 800B3FA4 000AFDE4 48 00 00 08 */ b lbl_800B3FAC .global lbl_800B3FA8 lbl_800B3FA8: /* 800B3FA8 000AFDE8 C0 22 8B 78 */ lfs f1, "@6934"@sda21(r2) .global lbl_800B3FAC lbl_800B3FAC: /* 800B3FAC 000AFDEC D0 21 00 10 */ stfs f1, 0x10(r1) /* 800B3FB0 000AFDF0 38 A1 00 08 */ addi r5, r1, 0x8 /* 800B3FB4 000AFDF4 48 04 AE 9D */ bl MTX34Scale__Q24nw4r4mathFPQ34nw4r4math5MTX34PCQ34nw4r4math5MTX34PCQ34nw4r4math4VEC3 /* 800B3FB8 000AFDF8 80 01 00 24 */ lwz r0, 0x24(r1) /* 800B3FBC 000AFDFC 7C 08 03 A6 */ mtlr r0 /* 800B3FC0 000AFE00 38 21 00 20 */ addi r1, r1, 0x20 /* 800B3FC4 000AFE04 4E 80 00 20 */ blr /* 800B3FC8 000AFE08 00 00 00 00 */ .4byte 0x00000000 /* 800B3FCC 000AFE0C 00 00 00 00 */ .4byte 0x00000000 .global MTXColLen__Q24nw4r2efFPCQ34nw4r4math5MTX34i MTXColLen__Q24nw4r2efFPCQ34nw4r4math5MTX34i: /* 800B3FD0 000AFE10 54 84 10 3A */ slwi r4, r4, 2 /* 800B3FD4 000AFE14 7C 83 22 14 */ add r4, r3, r4 /* 800B3FD8 000AFE18 E0 04 80 00 */ psq_l f0, 0x0(r4), 1, qr0 /* 800B3FDC 000AFE1C E0 24 80 10 */ psq_l f1, 0x10(r4), 1, qr0 /* 800B3FE0 000AFE20 C0 44 00 20 */ lfs f2, 0x20(r4) /* 800B3FE4 000AFE24 10 00 0C 20 */ ps_merge00 f0, f0, f1 /* 800B3FE8 000AFE28 10 00 00 32 */ ps_mul f0, f0, f0 /* 800B3FEC 000AFE2C 10 22 00 BA */ ps_madd f1, f2, f2, f0 /* 800B3FF0 000AFE30 EC 40 00 28 */ fsubs f2, f0, f0 /* 800B3FF4 000AFE34 10 21 00 14 */ ps_sum0 f1, f1, f0, f0 /* 800B3FF8 000AFE38 FC 01 10 00 */ fcmpu cr0, f1, f2 /* 800B3FFC 000AFE3C 4D 82 00 20 */ beqlr /* 800B4000 000AFE40 FC 00 08 34 */ frsqrte f0, f1 /* 800B4004 000AFE44 3C C0 80 55 */ lis r6, sPS_Three_Half__Q24nw4r2ef@ha /* 800B4008 000AFE48 38 C6 69 60 */ addi r6, r6, sPS_Three_Half__Q24nw4r2ef@l /* 800B400C 000AFE4C E0 66 00 00 */ psq_l f3, 0x0(r6), 0, qr0 /* 800B4010 000AFE50 EC 40 00 32 */ fmuls f2, f0, f0 /* 800B4014 000AFE54 10 00 00 DA */ ps_muls1 f0, f0, f3 /* 800B4018 000AFE58 EC 42 18 7C */ fnmsubs f2, f2, f1, f3 /* 800B401C 000AFE5C EC 02 00 32 */ fmuls f0, f2, f0 /* 800B4020 000AFE60 EC 21 00 32 */ fmuls f1, f1, f0 /* 800B4024 000AFE64 4E 80 00 20 */ blr /* 800B4028 000AFE68 00 00 00 00 */ .4byte 0x00000000 /* 800B402C 000AFE6C 00 00 00 00 */ .4byte 0x00000000 .include "macros.inc" .section .sdata, "wa" # 0x80556420 - 0x8055C6E0 ; 0x000062C0 .global sPS_Three_Half__Q24nw4r2ef sPS_Three_Half__Q24nw4r2ef: .4byte 0x40400000 .4byte 0x3F000000 .4byte 0 .4byte 0 .4byte 0 .4byte 0 .4byte 0 .4byte 0 .include "macros.inc" .section .sdata2, "wa" # 0x8055DF80 - 0x805643C0 ; 0x00006440 .global "@6727" "@6727": .4byte 0x47800000 .4byte 0x47800000 .global "@6728" "@6728": .4byte 0x4222F983 .global "@6743" "@6743": .4byte 0x3F800000 .global "@6744" "@6744": .4byte 0x34000000 .global "@6745" "@6745": .4byte 0 .global "@6793_8055EAD8" "@6793_8055EAD8": .4byte 0x00800000 .global "@6794_8055EADC" "@6794_8055EADC": .4byte 0xBF800000 .global "@6866" "@6866": .4byte 0xBFF00000 .4byte 0 .global "@6871" "@6871": .4byte 0x3F000000 .global "@6872" "@6872": .4byte 0x40400000 .global "@6879" "@6879": .4byte 0x47800000 .global "@6916" "@6916": .4byte 0x3727C5AC .global "@6934" "@6934": .4byte 0x47C35000 .global EMITTER_ZERO_SCALE__Q24nw4r2ef EMITTER_ZERO_SCALE__Q24nw4r2ef: .4byte 0x3727C5AC